SPC5604PGF0MLL6

Manufacturer Part NumberSPC5604PGF0MLL6
DescriptionIC MCU 32BIT 512KB FLASH 100LQFP
ManufacturerFreescale Semiconductor
SeriesMPC56xx Qorivva
SPC5604PGF0MLL6 datasheet
 


Specifications of SPC5604PGF0MLL6

Core Processore200z0hCore Size32-Bit
Speed64MHzConnectivityCAN, FlexRay, LIN, SPI, UART/USART
PeripheralsDMA, POR, PWM, WDTNumber Of I /o68
Program Memory Size512KB (512K x 8)Program Memory TypeFLASH
Eeprom Size64K x 8Ram Size40K x 8
Voltage - Supply (vcc/vdd)3 V ~ 5.5 VData ConvertersA/D 30x10b
Oscillator TypeInternalOperating Temperature-40°C ~ 125°C
Package / Case100-LQFPLead Free Status / RoHS StatusLead free / RoHS Compliant
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Freescale Semiconductor
Data Sheet: Technical Data
MPC5604P Microcontroller
Data Sheet
Up to 64 MHz, single issue, 32-bit CPU core
complex (e200z0h)
— Compliant with Power Architecture embedded
category
— Variable Length Encoding (VLE)
Memory organization
— Up to 512 KB on-chip code flash memory with
ECC and erase/program controller
— Optional 64 (4 × 16) KB on-chip data flash
memory with ECC for EEPROM emulation
— Up to 40 KB on-chip SRAM with ECC
Fail safe protection
— Programmable watchdog timer
— Non-maskable interrupt
— Fault collection unit
Nexus L2+ interface
Interrupts
— 16-channel eDMA controller
— 16 priority level controller
General purpose I/Os individually programmable as
input, output or special function
2 general purpose eTimer units
— 6 timers each with up/down count capabilities
— 16-bit resolution, cascadable counters
— Quadrature decode with rotation direction flag
— Double buffer input capture and output compare
Communications interfaces
— 2 LINFlex channels (LIN 2.1)
— 4 DSPI channels with automatic chip select
generation
— 1 FlexCAN interface (2.0B Active) with 32
message objects
— 1 safety port based on FlexCAN with 32
message objects and up to 7.5 Mbit/s capability;
Freescale reserves the right to change the detail specifications as may be required to permit
improvements in the design of its products.
© Freescale Semiconductor, Inc., 2008-2011. All rights reserved.
Document Number: MPC5604P
Rev. 7, 04/2011
MPC5604P
144 LQFP
20 mm x 20 mm
100 LQFP
14 mm x 14 mm
usable as second CAN when not used as safety
port
— 1 FlexRay™ module (V2.1) with selectable dual
or single channel support, 32 message objects
and up to 10 Mbit/s
Two 10-bit analog-to-digital converters (ADC)
— 2 × 15 input channels, 4 channels shared
between the two ADCs
— Conversion time < 1 µs including sampling time
at full precision
— Programmable Cross Triggering Unit (CTU)
— 4 analog watchdogs with interrupt capability
On-chip CAN/UART bootstrap loader with Boot
Assist Module (BAM)
1 FlexPWM unit
— 8 complementary or independent outputs with
ADC synchronization signals
— Polarity control, reload unit
— Integrated configurable dead time unit and
inverter fault input pins
— 16-bit resolution, up to 2 × f
— Lockable configuration
Clock generation
— 4–40 MHz main oscillator
— 16 MHz internal RC oscillator
— Software controlled FMPLL capable of speeds
as fast as 64 MHz
Voltage supply
— 3.3 V or 5 V supply for I/Os and ADC
— On-chip single supply voltage regulator with
external ballast transistor
Operating temperature ranges: –40 to 125 °C or –40
to 105 °C
CPU

SPC5604PGF0MLL6 Summary of contents

  • Page 1

    ... FlexCAN with 32 message objects and up to 7.5 Mbit/s capability; Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. © Freescale Semiconductor, Inc., 2008-2011. All rights reserved. Document Number: MPC5604P Rev. 7, 04/2011 MPC5604P ...

  • Page 2

    ... External interrupt timing (IRQ pin 3.17.5 DSPI timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 4 Package characteristics 4.1 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . 86 4.1.1 144 LQFP mechanical outline drawing 4.1.2 100 LQFP mechanical outline drawing Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Appendix AAbbreviations Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 MPC5604P Microcontroller Data Sheet, Rev. 7 Freescale Semiconductor ...

  • Page 3

    ... FlexRay FlexCAN (controller area network) Safety port FCU (fault collection unit) CTU (cross triggering unit) Freescale Semiconductor Table 1. MPC5604P device comparison MPC5603P 384 VLE (variable length encoding) 1 (includes four 32-bit timers) Yes (via second FlexCAN module) MPC5604P Microcontroller Data Sheet, Rev ...

  • Page 4

    ... MPC5604P MCU. 4 MPC5603P 8 (capturing on X-channels) 3 single supply with external transistor MPC5604P Microcontroller Data Sheet, Rev. 7 MPC5604P 2 (16-bit, 6 channels (10-bit, 15-channel ) 2 4 Yes Yes Yes (Level 2+) 3 MHz 4–40 MHz 100 LQFP 144 LQFP –40 to 125 °C Freescale Semiconductor ...

  • Page 5

    ... FCU Fault collection unit Flash Flash memory FlexCAN Controller area network FlexPWM Flexible pulse width modulation FMPLL Frequency-modulated phase-locked loop INTC Interrupt controller JTAG JTAG controller Freescale Semiconductor e200z0 Core 32-bit general purpose registers Integer Special Exception execution purpose unit registers ...

  • Page 6

    ... Interface between the system bus and on-chip peripherals Reduces the overall power consumption by disconnecting parts of the device from the power supply via a power switching device; device components are grouped into sections called “power domains” which are controlled by the PCU MPC5604P Microcontroller Data Sheet, Rev. 7 Function Freescale Semiconductor ...

  • Page 7

    ... Extensive system development support through Nexus debug port • Non-maskable interrupt support Freescale Semiconductor Function half-bridge power stage and two fault input channels Centralizes reset sources and manages the device reset sequence of the device Provides storage for program code, constants, and variables ...

  • Page 8

    ... Flash memory The MPC5604P provides as much as 576 KB of programmable, non-volatile, flash memory. The non-volatile memory (NVM) can be used for instruction and/or data storage. The flash memory module interfaces the system bus to a dedicated flash memory 8 MPC5604P Microcontroller Data Sheet, Rev. 7 Freescale Semiconductor ...

  • Page 9

    ... Typical SRAM access time: 0 wait-state for reads and 32-bit writes; 1 wait state for 8- and 16-bit writes if back to back with a read to same memory block 1.5.6 Interrupt controller (INTC) The interrupt controller (INTC) provides priority-based preemptive scheduling of interrupt requests, suitable for statically scheduled hard real-time systems. The INTC handles 147 selectable-priority interrupt sources. Freescale Semiconductor MPC5604P Microcontroller Data Sheet, Rev ...

  • Page 10

    ... The FMPLL allows the user to generate high speed system clocks from a 4–40 MHz input clock. Further, the FMPLL supports programmable frequency modulation of the system clock. The PLL multiplication factor, output clock divider ratio are all software configurable. The PLL has the following major features: • Input clock frequency: 4–40 MHz 10 MPC5604P Microcontroller Data Sheet, Rev. 7 Freescale Semiconductor ...

  • Page 11

    ... One 32-bit up counter with 8-bit prescaler • Four 32-bit compare channels • Independent interrupt source for each channel • Counter can be stopped in debug mode 1.5.14 Software watchdog timer (SWT) The SWT has the following features: Freescale Semiconductor MPC5604P Microcontroller Data Sheet, Rev ...

  • Page 12

    ... FlexCAN or LINFlex (using the boot assist module software). A censorship scheme is provided to protect the content of the flash memory and offer increased security for the entire device. A password mechanism is designed to grant the legitimate user access to the non-volatile memory. 12 MPC5604P Microcontroller Data Sheet, Rev. 7 Freescale Semiconductor ...

  • Page 13

    ... The FlexCAN module provides the following features: • Full implementation of the CAN protocol specification, version 2.0B — Standard data and remote frames — Extended data and remote frames — 8-bytes data length — Programmable bit rate Mbit/s Freescale Semiconductor MPC5604P Microcontroller Data Sheet, Rev ...

  • Page 14

    ... Dual channel or single channel mode of operation, each as fast as 10 Mbit/s data rate • Message buffers configurable as Tx RxFIFO • Message buffer size configurable • Message filtering for all message buffers based on FrameID, cycle count and message ID • Programmable acceptance filters for RxFIFO message buffers 14 MPC5604P Microcontroller Data Sheet, Rev. 7 Freescale Semiconductor ...

  • Page 15

    ... Programmable clock polarity and phase • End-of-transmission interrupt flag • Programmable transfer baud rate • Programmable data frames from bits • chip select lines available — DSPI_0 — 4 each on DSPI_1, DSPI_2 and DSPI_3 Freescale Semiconductor MPC5604P Microcontroller Data Sheet, Rev ...

  • Page 16

    ... Capture capability for PWMA, PWMB, and PWMX channels not supported 1.5.26 eTimer The MPC5604P includes two eTimer modules. Each module provides six 16-bit general purpose up/down timer/counter units with the following features: • Maximum operating clock frequency of 120 MHz • Individual channel capability 16 MPC5604P Microcontroller Data Sheet, Rev. 7 Freescale Semiconductor ...

  • Page 17

    ... ADC results against predefined levels (low, high, range) before results are stored in the appropriate ADC result location, • 2 modes of operation: Normal mode or CTU control mode • Normal mode features — Register-based interface with the CPU: control register, status register, 1 result register per channel Freescale Semiconductor DDIO MPC5604P Microcontroller Data Sheet, Rev. 7 DDIO 17 ...

  • Page 18

    ... Program trace messaging — Real time read/write of any internally memory mapped resources through JTAG pins — Overrun control, which selects whether to stall before Nexus overruns or keep executing and allow overwrite of information 18 (no dedicated power supply) DDIO MPC5604P Microcontroller Data Sheet, Rev. 7 Freescale Semiconductor ...

  • Page 19

    ... On-chip voltage regulator (VREG) The on-chip voltage regulator module provides the following features: • Uses external NPN (negative-positive-negative) transistor • Regulates external 3.3 V /5.0 V down to 1.2 V for the core logic • Low voltage detection on the internal 1.2 V and I/O voltage 3.3 V Freescale Semiconductor ...

  • Page 20

    ... D[14] 104 G[3] 103 C[14] 102 G[2] 101 C[13] 100 G[4] 99 D[12] 98 G[6] 97 VDD_HV_FL 96 VSS_HV_FL 95 D[13] 94 VSS_LV_COR1 93 VDD_LV_COR1 92 A[3] 91 VDD_HV_IO2 90 VSS_HV_IO2 89 TDO 88 TCK 87 TMS 86 TDI 85 G[5] 84 A[2] 83 G[7] 82 C[12] 81 G[8] 80 C[11] 79 G[9] 78 D[11] 77 G[10] 76 D[10] 75 G[11] 74 A[1] 73 A[0] Freescale Semiconductor ...

  • Page 21

    ... The following sections provide signal descriptions and related information about the functionality and configuration of the MPC5604P devices. 2.2.1 Power supply and reference voltage pins Table 3 lists the power supply and reference voltage for the MPC5604P devices. Freescale Semiconductor NMI 1 A[6] 2 D[1] ...

  • Page 22

    ... V Decoupling pins for core logic. Decoupling capacitor DD_LV_COR0 must be connected between these pins and the nearest V SS_LV_COR 22 Table 3. Supply pins Supply Description . . Five pairs ( available on 100-pin package pin. MPC5604P Microcontroller Data Sheet, Rev. 7 Pin 100-pin 144-pin — 6 — 126 88 127 Freescale Semiconductor ...

  • Page 23

    ... Dedicated pins. Available on 100-pin and 144-pin package. MDO[0] Nexus Message Data Output—line 0 NMI Non-Maskable Interrupt XTAL Analog output of the oscillator amplifier circuit; needs to be grounded if oscillator is used in bypass mode Freescale Semiconductor Table 3. Supply pins (continued) Supply Description pin. pin. pin. pin. pin. ...

  • Page 24

    ... Bidirectional Test pin, available on 100-pin and 144-pin package. — MPC5604P Microcontroller Data Sheet, Rev Pad speed Pin SRC = 0 SRC = 1 100-pin 144-pin — — Slow Fast 59 87 Slow — Slow Medium 58 86 Slow Fast 61 89 Medium — — — 74 107 Freescale Semiconductor ...

  • Page 25

    ... ALT0 ALT1 ALT2 ALT3 — A[6] PCR[6] ALT0 ALT1 ALT2 ALT3 — A[7] PCR[7] ALT0 ALT1 ALT2 ALT3 — Freescale Semiconductor Table 5. Pin muxing 3 Functions Peripheral 1,2 direction Port A (16-bit) GPIO[0] SIUL ETC[0] eTimer_0 SCK DSPI_2 F[0] FCU_0 EIRQ[0] SIUL GPIO[1] ...

  • Page 26

    ... Medium 81 118 I/O I/O I/O I I/O Slow Medium 82 120 I/O I/O I/O I I/O Slow Medium 83 122 O I/O I/O I I/O Slow Medium 95 136 — I/O — I/O Slow Medium 99 143 O I/O — I I/O Slow Medium 100 144 — I/O — Freescale Semiconductor 12 ...

  • Page 27

    ... ALT3 — — B[8] PCR[24] ALT0 ALT1 ALT2 ALT3 — — B[9] PCR[25] ALT0 ALT1 ALT2 ALT3 — Freescale Semiconductor Table 5. Pin muxing (continued) 3 Functions Peripheral 1,2 direction Port B (16-bit) GPIO[16] SIUL TXD FlexCAN_0 ETC[2] eTimer_1 DEBUG[0] SSCM EIRQ[15] SIUL GPIO[17] SIUL — ...

  • Page 28

    ... GPIO[33] SIUL Input only — — — — — — AN[2] ADC_0 MPC5604P Microcontroller Data Sheet, Rev Pad speed Pin No. I/O 4 SRC = 0 SRC = 1 — — 36 — — 37 — — 38 — — 42 — — 44 — — 43 — — 45 — — 28 Freescale Semiconductor ...

  • Page 29

    ... ALT1 ALT2 ALT3 — C[9] PCR[41] ALT0 ALT1 ALT2 ALT3 — C[10] PCR[42] ALT0 ALT1 ALT2 ALT3 — Freescale Semiconductor Table 5. Pin muxing (continued) 3 Functions Peripheral 1,2 direction GPIO[34] SIUL Input only — — — — — — AN[3] ADC_0 GPIO[35] ...

  • Page 30

    ... Slow Medium 71 101 I/O — — I/O Slow Medium 72 103 I/O O — I/O Slow Symmetric 85 124 O I/O I I/O Slow Symmetric 86 125 O I/O I/O I/O Slow Medium 3 — I I/O Slow Medium 97 140 — I/O I/O I I/O Slow Symmetric 89 128 O I/O O Freescale Semiconductor ...

  • Page 31

    ... D[11] PCR[59] ALT0 ALT1 ALT2 ALT3 D[12] PCR[60] ALT0 ALT1 ALT2 ALT3 — D[13] PCR[61] ALT0 ALT1 ALT2 ALT3 Freescale Semiconductor Table 5. Pin muxing (continued) 3 Functions Peripheral 1,2 direction GPIO[52] SIUL CB_TR_EN FlexRay_0 ETC[5] eTimer_1 B[3] FlexPWM_0 GPIO[53] SIUL CS3 DSPI_0 ...

  • Page 32

    ... AN[8] ADC_0 MPC5604P Microcontroller Data Sheet, Rev Pad speed Pin No. I/O 4 SRC = 0 SRC = 1 I/O Slow Medium 73 105 I/O O — I — — 41 — — 46 — — 27 — — 32 — — — — — — — — — Freescale Semiconductor ...

  • Page 33

    ... ALT1 ALT2 ALT3 — E[13] PCR[77] ALT0 ALT1 ALT2 ALT3 — E[14] PCR[78] ALT0 ALT1 ALT2 ALT3 — Freescale Semiconductor Table 5. Pin muxing (continued) 3 Functions Peripheral 1,2 direction GPIO[70] SIUL Input only — — — — — — AN[9] ADC_0 GPIO[71] ...

  • Page 34

    ... Medium — O I/O — I/O Slow Fast — O — — I/O Slow Fast — O — — I/O Slow Fast — O — — I/O Slow Fast — O — — I/O Slow Fast — O — — Freescale Semiconductor 121 133 135 137 139 ...

  • Page 35

    ... PCR[96] ALT0 ALT1 ALT2 ALT3 — G[1] PCR[97] ALT0 ALT1 ALT2 ALT3 — G[2] PCR[98] ALT0 ALT1 ALT2 ALT3 Freescale Semiconductor Table 5. Pin muxing (continued) 3 Functions Peripheral 1,2 direction GPIO[89] SIUL MSEO0 NEXUS_0 — — — — GPIO[90] SIUL EVTO NEXUS_0 — ...

  • Page 36

    ... O — — I/O Slow Medium — O — — I/O Slow Medium — — — — I I/O Slow Medium — — — — I I/O Slow Medium — — — — I I/O Slow Medium — — — — I Freescale Semiconductor 104 100 ...

  • Page 37

    ... Multiple inputs are routed to all respective modules internally. The input of some modules must be configured by setting the values of the PSMI[PADSELx] bitfields inside the SIUL module. 5 Programmable via the SRC (Slew Rate Control) bits in the respective Pad Configuration Register. 6 Weak pull down during reset. Freescale Semiconductor MPC5604P Microcontroller Data Sheet, Rev ...

  • Page 38

    ... D Those parameters are derived mainly from simulations. The classification is shown in the column labeled “C” in the parameter tables where appropriate. 38 CAUTION Table 6. Parameter classifications Tag description NOTE MPC5604P Microcontroller Data Sheet, Rev This can be done by the DD SS Freescale Semiconductor ...

  • Page 39

    ... SR ADC_1 ground and low reference SS_HV_ADC1 voltage with respect to ground ( Slope characteristics on all V DD during power up ground ( Voltage on any pin with respect to IN ground (V SS_HV_IOx ground (V SS Freescale Semiconductor Table 7. Absolute maximum ratings Parameter Conditions — — — — Relative to V DD_HV_IOx — ...

  • Page 40

    ... Parameter Conditions — — — — — VDD_HV_xxx –0.3 V MPC5604P Microcontroller Data Sheet, Rev (continued) Value 2 Min Max –10 10 –50 50 — 155 –55 150 –40 150 – < 300 mV. DD_HV_ADC1 DD_HV_ADC0 VDD_HV_IOx 6.0 V  6 DD_HV_IOx DD_HV Freescale Semiconductor Unit °C °C supply. ...

  • Page 41

    ... DD_HV_FL supply voltage V SR Code and data flash ground SS_HV_FL V SR 5.0 V crystal oscillator amplifier DD_HV_OSC supply voltage V SR 5.0 V crystal oscillator amplifier SS_HV_OSC reference voltage Freescale Semiconductor 2.7 V Parameter Conditions — — — — Relative to V DD_HV_IOx — — Relative to ...

  • Page 42

    ... DD_HV_REG 0 0 4.5 5.5 V – 0.1 — DD_HV_REG 0 0 — — — — –40 125 – V DD_HV_IOy DD_HV_IOx  < 100 mV. DD_HV_ADC1 DD_HV_ADC0 ) must SS_LV_xxx ) must be connected DD_LV_xxx and V are internally shorted. SS_LV_COR2 and V SS_LV_REGCOR SS_LV_CORx Freescale Semiconductor Unit °C | < . ...

  • Page 43

    ... Parametric figures can be out of specification when voltage drops below 4.5 V, however, guaranteeing the full functionality. In particular, ADC electrical characteristics and I/Os DC electrical specification may not be guaranteed. 2 The difference between each couple of voltage supplies must be less than 100 mV, |V 100 mV. Freescale Semiconductor Parameter Conditions — — — ...

  • Page 44

    ... SS_LV_COR1 are physically shorted internally, as are V VDD_HV_xxx 3.0 V 3.3 V MPC5604P Microcontroller Data Sheet, Rev. 7 – V DD_HV_ADC1 DD_HV_ADC0 ) must SS_LV_xxx ) must be connected DD_LV_xxx and V are internally shorted. SS_LV_COR2 and V SS_LV_REGCOR SS_LV_CORx VDD_HV_IOx 5.5 V  5 DD_HV_IOx DD_HV Freescale Semiconductor | . supply. ...

  • Page 45

    ... Thermal characterization parameter indicating the temperature difference between the board and the junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written as Psi-JB. Freescale Semiconductor 3.0 V Parameter Conditions Single layer board—1s 1 Four layer board— ...

  • Page 46

    ... Equation  Equation 2 as the sum of a junction to case thermal resistance JA JC CA MPC5604P Microcontroller Data Sheet, Rev. 7 Typical value Unit 47.3 °C/W 35.3 °C/W 19.1 °C/W 9.7 °C/W 19.1 °C/W 0.8 °C/W 1: Eqn. 1 Eqn. 2 Freescale Semiconductor ...

  • Page 47

    ... G. Kromann, S. Shidore, and S. Addison, Thermal Modeling of a PBGA for Air-Cooled Applications, Electronic Packaging and Production, pp. 53–58, March 1998 Joiner and V. Adams, Measurement and Simulation of Junction to Board Thermal Resistance and Its Application in Thermal Modeling, Proceedings of SemiTherm, San Diego, 1999, pp. 212–220. Freescale Semiconductor Equation ( ...

  • Page 48

    ... MHz 16 dBµV 150–1000 MHz 15 IEC Level M — 150 kHz–150 MHz 15 dBµV 150–1000 MHz 14 IEC Level M — Conditions Value Unit — 2000 V — 750 (corners) V 500 (other) /V supply pairs DD_LV_CORx SS_LV_CORx Freescale Semiconductor ...

  • Page 49

    ... R SR — Resulting ESR of all four C REG C SR — External decoupling/stability DEC2 ceramic capacitor C SR — External decoupling/stability DEC3 ceramic capacitor on VDD_HV_REG Freescale Semiconductor VDD_HV_REG BCTRL VDD_LV_COR C DEC2 Parameter Conditions Post-trimming 4 capacitances Absolute maximum DEC1 value between 100 kHz and 10 MHz ...

  • Page 50

    ... MPC5604P Microcontroller Data Sheet, Rev DEC3 BCP68, BCX68, BC817SU C DEC1 Value Min Typ Max 1.15 — 1.32 18 — 22 — 19.5 30 — 14.3 22 — — — 45 1200 1760 — 2 × 10 — — Freescale Semiconductor Unit V k µF µF m nF µF ...

  • Page 51

    ... A POWER_OK signal is generated when all critical supplies monitored by the LVD are available. This signal is active high and released to all modules including I/Os, flash memory and RC16 oscillator needed during power-up phase and reset phase. When POWER_OK is low the associated module are set into a safe state. Freescale Semiconductor voltage while device is supplied: DD_LV Parameter = – ...

  • Page 52

    ... Internal Reset Generation Module FSM IDLE LVDHV3H PORH POR_UP V MLVDOK_H ~1us P0 Figure 10. Power-up typical sequence V LVDHV3L V PORH P0 Figure 11. Power-down typical sequence MPC5604P Microcontroller Data Sheet, Rev. 7 3.3V 0V 3.3V 0V 3.3V 0V 1.2V 0V 3.3V 0V 3.3V 0V 1. 3.3V 0V 3.3V 0V 3.3V 0V 1.2V 0V 3.3V 0V 3.3V 0V 1.2V 0V 1.2V 0V Freescale Semiconductor ...

  • Page 53

    ... High voltage supply is 3 Default manufacturing value before flash initialization is ‘1’ (3.3 V). 3.10.1.2 NVUSRO[OSCILLATOR_MARGIN] field description The fast external crystal oscillator consumption is dependent on the OSCILLATOR_MARGIN bit value. NVUSRO[OSCILLATOR_MARGIN] controls the device configuration. Freescale Semiconductor V V LVDHV3H LVDHV3L ~1us P0 Figure 12. Brown-out typical sequence Table 17 ...

  • Page 54

    ... V — DD_HV_IOx — 0.1 V DD_HV_IOx 0.8 V — DD_HV_IOx — 0.1 V DD_HV_IOx 0.8 V — DD_HV_IOx — 0.1 V DD_HV_IOx 0.8 V — DD_HV_IOx –130 — — –10 10 — — 130 –1 1 –0.5 0.5 — 10 Table 7. Freescale Semiconductor Figure 13. Unit µA µA µA µA pF ...

  • Page 55

    ... OFF, OSC/PLL_0/PLL_1 are OFF, core clock frozen, all peripherals are disabled. 3.10.3 DC electrical characteristics (3.3 V) Table 21 gives the DC electrical characteristics at 3.3 V (3.0 V < V Figure 13. Table 21. DC electrical characteristics (3.3 V, NVUSRO[PAD3V5V Symbol C Parameter V D Low level input voltage IL P Freescale Semiconductor Parameter 1 V DD_LV_CORx externally forced at 1 DD_LV_CORx externally forced at 1 DD_LV_CORx externally forced at 1 ...

  • Page 56

    ... DD_HV_IOx — 0.5 V – 0.8 — DD_HV_IOx — 0.5 V – 0.8 — DD_HV_IOx — 0.5 V – 0.8 — DD_HV_IOx –130 — — –10 10 — — 130 — 1 — 0.5 — 10 Table 7. Freescale Semiconductor Unit µA µA µA µA pF ...

  • Page 57

    ... STOP “P” mode Device Under Test (DUT) configuration: code fetched from RAM, code and data flash memories OFF, OSC/PLL_0/PLL_1 are OFF, core clock frozen, all peripherals are disabled. 3.10.4 Input DC electrical characteristics definition Figure 13 shows the DC electrical characteristics behavior as function of time. Freescale Semiconductor Parameter 1 V DD_LV_CORx externally forced at 1.3 V ...

  • Page 58

    ... Pad NMI PAD[6] PAD[49] PAD[84] PAD[85] 58 Table 23. I/O supply segment Supply segment Table 24. I/O weight 144 LQFP Weight 5V Weight 3. 14% 10 MPC5604P Microcontroller Data Sheet, Rev HYS /V supply pair — 100 LQFP Weight 5V Weight 3. 14% 13% 14% 12% — — — — Freescale Semiconductor ...

  • Page 59

    ... PAD[8] PAD[37] PAD[5] PAD[39] PAD[35] PAD[87] PAD[88] PAD[89] PAD[90] PAD[91] PAD[57] PAD[56] PAD[53] PAD[54] PAD[55] PAD[96] PAD[65] PAD[67] PAD[33] PAD[68] PAD[23] PAD[69] PAD[34] PAD[70] PAD[24] PAD[71] PAD[66] PAD[25] PAD[26] Freescale Semiconductor Table 24. I/O weight (continued) 144 LQFP Weight 5V Weight 10% 7% ...

  • Page 60

    ... MPC5604P Microcontroller Data Sheet, Rev. 7 100 LQFP Weight 5V Weight 3. — — — — — — — — — — 23% 20% 21% 18% — — 19% 16% — — 17% 15% — — 15% 13% — — 13% 12% — — 11% 10% — — 10 16% 11 — — Freescale Semiconductor ...

  • Page 61

    ... PAD[17] PAD[42] PAD[93] PAD[95] PAD[18] PAD[94] PAD[19] PAD[77] PAD[10] PAD[78] PAD[11] PAD[79] PAD[12] PAD[41] PAD[47] PAD[48] PAD[51] PAD[52] PAD[40] PAD[80] PAD[9] PAD[81] Freescale Semiconductor Table 24. I/O weight (continued) 144 LQFP Weight 5V Weight 3.3V 11% 10% 12% 10% 12% 10% 12% 11% 12% 11% 13% 11% 13% 11% 13% 12% 1% ...

  • Page 62

    ... MPC5604P Microcontroller Data Sheet, Rev. 7 100 LQFP Weight 5V Weight 3.3V 12% 11% — — 13% 12% — — 14% 12% — — 14% 13% 14% 13% 15% 13% Value Unit Min Max 4 40 MHz 6.5 25 mA/V 1 — — ms Value Unit Min Max 4 40 MHz 4 20 mA/V 1 — — ms Freescale Semiconductor ...

  • Page 63

    ... V ±10%; V DD_LV_CORx 2 Considering operation with PLL not bypassed 3 “Loss of Reference Frequency” window is the reference frequency range outside of which the PLL is in self-clocked mode. Freescale Semiconductor Table 27. Input clock characteristics Parameter Table 28. FMPLL electrical characteristics Conditions 2 Crystal reference Measured using clock division — ...

  • Page 64

    ... DDPLL SSPLL Parameter °C in high-frequency from the MPC5604P Microcontroller Data Sheet, Rev. 7 and JITTER is 2% (above 64 MHz). CS Value Conditions Unit Min Typ Max °C — 16 — MHz A — –5 — °C –1 — °C — 1.6 — Freescale Semiconductor ...

  • Page 65

    ... The filter at the input pins must be designed taking into account the dynamic characteristics of the input signal (bandwidth) and the equivalent input impedance of the ADC itself. Freescale Semiconductor (2) (1) ...

  • Page 66

    ... Figure 15. Input equivalent circuit (refer to the equivalent circuit reported in A MPC5604P Microcontroller Data Sheet, Rev. 7 being the external circuit  LSB 2 INTERNAL CIRCUIT SCHEME V DD Channel Sampling Selection R R SW1 and Figure 15): A charge sharing phenomenon Freescale Semiconductor = 1 EQ Eqn are P2 ...

  • Page 67

    ... The charge of C and C is redistributed also according to Equation 7: • A second charge transfer involves also again considering the worst case in which C L would be faster), the time constant is: Freescale Semiconductor Voltage Transient V <0.5 LSB 2  1  (call ...

  • Page 68

    ... Equation 10 must be respected (charge A1    filter, is not able the time constant conversion Rate longer than the sampling time definitively much higher than the F F Equation 11 between the ideal and real sampled Freescale Semiconductor Eqn Eqn ...

  • Page 69

    ... R — D Internal resistance of analog source SW1 7 R — D Internal resistance of analog source AD I — T Input current injection INJ INL CC P Integral non-linearity DNL CC P Differential non-linearity OSE CC T Offset error Freescale Semiconductor ----------- - = ------------------------------------------------------- - maximum, that is for instance 5 V), assuming to accept a maximum error of ...

  • Page 70

    ... After the ADC_S Value Initial 1 3 Typical Max 2 max — 500 — 1.45 1.65 33 — 0.18 0.21 4.10 — 300 500 5000 — 400 600 5000 — 800 1300 7500 Freescale Semiconductor Unit LSB LSB LSB Unit µ ...

  • Page 71

    ... DD 3.16 AC specifications 3.16.1 Pad AC specifications Symbol C Parameter Output transition time output pin tr SLOW configuration Freescale Semiconductor Table 32. Flash memory module life Parameter Conditions ) Blocks with 0–1,000 P/E 1 cycles Blocks with 10,000 P/E cycles Blocks with 100,000 P/E cycles Table 33. Flash memory read access timing Parameter = – ...

  • Page 72

    ... Min Typ Max = 5.0 V ± 10%, — — — — 20 — — 3.3 V ± 10%, — — — — 25 — — 5.0 V ± 10%, — — — — 6 — — 3.3 V ± 10%, — — — — 7 — — 12 — — 4 — — DD_HV_IOx Freescale Semiconductor Unit ...

  • Page 73

    ... device reset forced by V RESET filtered by filtered by lowpass filter hysteresis W Freescale Semiconductor V device start-up phase RESET T POR Figure 19. Start-up reset requirements unknown reset filtered by state lowpass filter W FRST FRST W NFRST Figure 20. Noise filtering on reset signal MPC5604P Microcontroller Data Sheet, Rev. 7 hw_rst ‘ ...

  • Page 74

    ... V DD 0.1V — — — — 0. — — 0. — — 0.5 — — — — 20 — — 40 — — 12 — — 25 — — 40 — — 500 — — ns — — — 150 µA 10 — 150 4 10 — 250 Freescale Semiconductor ...

  • Page 75

    ... D Boundary scan input valid to TCK rising edge BSDST TCK rising edge to boundary scan input invalid BSDHT TCK 3 Freescale Semiconductor = only transient configuration during power-up. All pads but RESET DD Parameter DD_HV_IOx 1 Figure 21. JTAG test clock input timing MPC5604P Microcontroller Data Sheet, Rev. 7 Value ...

  • Page 76

    ... TCK TMS, TDI TDO Figure 22. JTAG test access port timing MPC5604P Microcontroller Data Sheet, Rev Freescale Semiconductor ...

  • Page 77

    ... D MCKO low to MDO data valid MDOV MCKO low to MSEO data valid MSEOV MCKO low to EVTO data valid EVTOV TCK cycle time TCYC Freescale Semiconductor Figure 23. JTAG boundary scan timing Table 37. Nexus debug port timing Parameter MPC5604P Microcontroller Data Sheet, Rev Value Unit Min ...

  • Page 78

    ... Figure 25. Nexus event trigger and test clock timings 78 1 Parameter Output Data Valid Figure 24. Nexus output timing 5 MPC5604P Microcontroller Data Sheet, Rev. 7 (continued) Value Unit Min Typ Max 6 — — 6 — — 10 — — 10 — — — — — — Freescale Semiconductor ...

  • Page 79

    ... D IRQ edge to edge time ICYC 1 IRQ timing specified at f SYS with SRC = 0b00. 2 Applies when IRQ pins are configured for rising edge or falling edge events, but not both. Freescale Semiconductor Figure 26. Nexus TDI, TMS, TDO timing Table 38. External interrupt timing Parameter Conditions ...

  • Page 80

    ... Master (MTFE = 0) Slave Master (MTFE = 1, CPHA = 0) Master (MTFE = 1, CPHA = 1) MPC5604P Microcontroller Data Sheet, Rev Value Min Max 60 — 60 — 16 — 26 — SCK SCK — 30 — — 13 — 35 — 4 — 35 — 35 — –5 — 4 — 11 — –5 — Freescale Semiconductor Unit ...

  • Page 81

    ... All timing is provided with 50 pF capacitance on output transition time on input signal. PCSx SCK Output (CPOL=0) SCK Output (CPOL=1) SIN SOUT Note: Numbers shown reference Figure 28. DSPI classic SPI timing – Master, CPHA = 0 Freescale Semiconductor 1 Table 39. DSPI timing (continued) Parameter Conditions Master (MTFE = 0) Slave Master (MTFE = 1, CPHA = 0) Master (MTFE = 1, CPHA = 1) ...

  • Page 82

    ... Note: Numbers shown reference Figure 30. DSPI classic SPI timing – Slave, CPHA = Data First Data 12 Data First Data Table 39 First Data Data Last Data 9 10 Data Last Data First Data Table 39. MPC5604P Microcontroller Data Sheet, Rev Last Data 11 Last Data Freescale Semiconductor ...

  • Page 83

    ... Figure 31. DSPI classic SPI timing – Slave, CPHA = 1 PCSx SCK Output (CPOL=0) SCK Output (CPOL=1) SIN SOUT Note: Numbers shown reference Figure 32. DSPI modified transfer format timing – Master, CPHA = 0 Freescale Semiconductor 11 5 Data First Data 9 10 Data First Data Table 39 ...

  • Page 84

    ... Note: Numbers shown reference Figure 34. DSPI modified transfer format timing – Slave, CPHA = First Data Data 12 First Data Data Table 39 First Data Data Last Data 10 9 Data Last Data First Data Table 39. MPC5604P Microcontroller Data Sheet, Rev Last Data 11 Last Data Freescale Semiconductor ...

  • Page 85

    ... SS SCK Input (CPOL=0) SCK Input (CPOL=1) SOUT SIN Note: Numbers shown reference Figure 35. DSPI modified transfer format timing – Slave, CPHA = 1 PCSS PCSx Note: Numbers shown reference Freescale Semiconductor 11 5 First Data Data 9 10 First Data Data Table 39. 7 Table 39. ...

  • Page 86

    ... Package characteristics 4.1 Package mechanical data 4.1.1 144 LQFP mechanical outline drawing L Figure 37. 144 LQFP package mechanical drawing (part 1) 86 MPC5604P Microcontroller Data Sheet, Rev. 7 Freescale Semiconductor ...

  • Page 87

    ... Figure 38. 144 LQFP package mechanical drawing (part 2) Freescale Semiconductor MPC5604P Microcontroller Data Sheet, Rev ...

  • Page 88

    ... LQFP mechanical outline drawing Figure 39. 100 LQFP package mechanical drawing (part 1) 88 MPC5604P Microcontroller Data Sheet, Rev. 7 Freescale Semiconductor ...

  • Page 89

    ... Figure 40. 100 LQFP package mechanical drawing (part 2) Freescale Semiconductor MPC5604P Microcontroller Data Sheet, Rev ...

  • Page 90

    ... Figure 41. 100 LQFP package mechanical drawing (part 3) 90 MPC5604P Microcontroller Data Sheet, Rev. 7 Freescale Semiconductor ...

  • Page 91

    ... E1 13.800 E3 — e — L 0.450 L1 — k 0.0° 2 ccc 1 Values in inches are converted from millimeters (mm) and rounded to four decimal digits. 2 Tolerance Freescale Semiconductor Table 40. Dimensions mm Typ Max — 1.600 — 0.150 1.400 1.450 0.220 0.270 — 0.200 16.000 16.200 14.000 14.200 12.000 — ...

  • Page 92

    ... 512 KB Product P = MPC560xP family Optional fields E = Data Flash (blank if none FlexRay (blank if none Data Flash + FlexRay MPC5604P Microcontroller Data Sheet, Rev Temperature spec –40 to 105 ° –40 to 125 °C Package Code LL = 100 LQFP LQ = 144 LQFP Frequency MHz MHz Freescale Semiconductor ...

  • Page 93

    ... NPN NVUSRO PTF PWM RBW SCK SOUT TCK TDI TDO TMS Freescale Semiconductor Table A-1. Abbreviations Meaning Complementary metal–oxide–semiconductor Clock phase Clock polarity Peripheral chip select Device under test Error code correction Event out General purpose input/output Modulus counter ...

  • Page 94

    ... Electrical parameters are identified as either system requirements or controller characteristics. Method used to guarantee each controller characteristic is noted in table. • AC Timings: 1149.1 (JTAG) Timing, Nexus Timing, External Interrupt Timing, and DSPI Timing sections deleted MPC5604P Microcontroller Data Sheet, Rev. 7 and V deleted. OH_SYM Freescale Semiconductor ...

  • Page 95

    ... Replaces whole section. Table 38 – Renamed the “Flash (KB)“ heading column in “Code Flash / Data Flash (EE) (KB)“ – Replaced the value of RAM from 32 to 36KB in the last four rows. Freescale Semiconductor Table 41. Revision history (continued) Substantive changes DSPI Timing sections inserted again. ...

  • Page 96

    ... DD_LV_PLL SS_LV_PLL SS_LV_COR3”. value A row to “Absolute Maximum Ratings“ table ”Voltage Regulator Electrical Characteristics” table. DEC2 into “Input Equivalent Circuit“ figure. S MPC5604P Microcontroller Data Sheet, Rev. 7 “ DD_LV_COR3 Freescale Semiconductor ...

  • Page 97

    ... V; is 1.145 V Section 3.10, “DC electrical Updated “NVUSRO[OSCILLATOR_MARGIN] field description Supply current (5.0 V, NVUSRO[PAD3V5V] = 0): updated symbols Freescale Semiconductor Table 41. Revision history (continued) Substantive changes list: updated descriptions of core and memory features “Introduction: changed title (was: Overview); reorganized contents Section 1.5, “Feature details ...

  • Page 98

    ... Pad output delay diagram A-1: Added abbreviations “DUT”, “NPN”, and “RBW” MPC5604P Microcontroller Data Sheet, Rev. 7 min value FMPLLOUT ADC_PU Freescale Semiconductor ...

  • Page 99

    ... Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer ...