SPC5604PGF0MLL6 Freescale Semiconductor, SPC5604PGF0MLL6 Datasheet - Page 7

• Manufacturer Part Number: SPC5604PGF0MLL6
• Description: IC MCU 32BIT 512KB FLASH 100LQFP
• Manufacturer: Freescale Semiconductor
• Series: MPC56xx Qorivvar

Specifications of SPC5604PGF0MLL6

• Core Processor: e200z0h
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CAN, FlexRay, LIN, SPI, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 68
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 64K x 8
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 30x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

1.5
1.5.1
The e200z0 Power Architecture core provides the following features:
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Pulse width modulator (FlexPWM) Contains four PWM submodules, each of which is capable of controlling a single
Reset generation module
(MC_RGM)
Static random-access memory
(SRAM)
System integration unit lite (SIUL) Provides control over all the electrical pad controls and up 32 ports with 16 bits
System status and configuration
module (SSCM)
System timer module (STM)
System watchdog timer (SWT)
Wakeup unit (WKPU)
AUTOSAR: AUTomotive Open System ARchitecture (see http://www.autosar.org)
High performance e200z0 core processor for managing peripherals and interrupts
Single issue 4-stage pipeline in-order execution 32-bit Power Architecture CPU
Harvard architecture
Variable length encoding (VLE), allowing mixed 16-bit and 32-bit instructions
— Results in smaller code size footprint
— Minimizes impact on performance
Branch processing acceleration using lookahead instruction buffer
Load/store unit
— 1 cycle load latency
— Misaligned access support
— No load-to-use pipeline bubbles
Thirty-two 32-bit general purpose registers (GPRs)
Separate instruction bus and load/store bus Harvard architecture
Hardware vectored interrupt support
Reservation instructions for implementing read-modify-write constructs
Long cycle time instructions, except for guarded loads, do not increase interrupt latency
Extensive system development support through Nexus debug port
Non-maskable interrupt support
Feature details
High performance e200z0 core processor
Block
Table 2. MPC5604P series block summary (continued)
MPC5604P Microcontroller Data Sheet, Rev. 7
half-bridge power stage and two fault input channels
Centralizes reset sources and manages the device reset sequence of the device
Provides storage for program code, constants, and variables
of bidirectional, general-purpose input and output signals and supports up to 32
external interrupts with trigger event configuration
Provides system configuration and status data (such as memory size and status,
device mode and security status), device identification data, debug status port
enable and selection, and bus and peripheral abort enable/disable
Provides a set of output compare events to support AUTOSAR
system tasks
Provides protection from runaway code
Supports up to 18 external sources that can generate interrupts or wakeup
events, 1 of which can cause non-maskable interrupt requests or wakeup events
Function
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and operating
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