AD962711-105EBZ Analog Devices Inc, AD962711-105EBZ Datasheet - Page 26

• Manufacturer Part Number: AD962711-105EBZ
• Description: EVAL For 11bit 105 Dual 1.8V
• Manufacturer: Analog Devices Inc

Specifications of AD962711-105EBZ

• Number Of Adc's: 2
• Number Of Bits: 11
• Sampling Rate (per Second): 105M
• Data Interface: Serial
• Inputs Per Adc: 1 Differential
• Input Range: 1 ~ 2 Vpp
• Power (typ) @ Conditions: 600mW @ 105MSPS
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: AD962711
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9627-11
External Reference Operation
The use of an external reference may be necessary to enhance
the gain accuracy of the ADC or improve thermal drift charac-
teristics. Figure 54 shows the typical drift characteristics of the
internal reference in 1.0 V mode.
When the SENSE pin is tied to AVDD, the internal reference is
disabled, allowing the use of an external reference. An internal
reference buffer loads the external reference with an equivalent
6 kΩ load (see Figure 15). The internal buffer generates the
positive and negative full-scale references for the ADC core.
Therefore, the external reference must be limited to a maximum
of 1.0 V.
CLOCK INPUT CONSIDERATIONS
For optimum performance, the AD9627-11 sample clock inputs,
CLK+ and CLK−, should be clocked with a differential signal.
The signal is typically ac-coupled into the CLK+ and CLK− pins
via a transformer or capacitors. These pins are biased internally
(see Figure 55) and require no external bias.
Clock Input Options
The AD9627-11 has a very flexible clock input structure. Clock
input can be a CMOS, LVDS, LVPECL, or sine wave signal.
Regardless of the type of signal being used, clock source jitter is
of the most concern, as described in the Jitter Considerations
section.
–0.5
–1.0
–1.5
–2.0
–2.5
2.5
2.0
1.5
1.0
0.5
CLK+
0
–40
Figure 55. Equivalent Clock Input Circuit
–20
2pF
Figure 54. Typical VREF Drift
0
TEMPERATURE (°C)
AVDD
1.2V
20
40
60
2pF
CLK–
80
Rev. A | Page 26 of 72
Figure 56 and Figure 57 show two preferred methods for clocking
the AD9627-11 (at clock rates up to 625 MHz). A low jitter clock
source is converted from a single-ended signal to a differential
signal using either an RF balun or an RF transformer.
The RF balun configuration is recommended for clock
frequencies between 125 MHz and 625 MHz, and the RF
transformer is recommended for clock frequencies from 10 MHz
to 200 MHz. The back-to-back Schottky diodes across the
transformer/balun secondary limit clock excursions into the
AD9627-11 to approximately 0.8 V p-p differential.
This helps prevent the large voltage swings of the clock from
feeding through to other portions of the AD9627-11 while
preserving the fast rise and fall times of the signal that are critical
to a low jitter performance.
If a low jitter clock source is not available, another option is to
ac-couple a differential PECL signal to the sample clock input
pins, as shown in Figure 58. The
AD9513/AD9514/AD9515/AD9516
jitter performance.
A third option is to ac-couple a differential LVDS signal to the
sample clock input pins, as shown in Figure 59. The AD9510/
AD9511/AD9512/AD9513/AD9514/AD9515/AD9516 clock
drivers offer excellent jitter performance.
CLOCK
CLOCK
CLOCK
INPUT
INPUT
INPUT
CLOCK
INPUT
Figure 56. Transformer-Coupled Differential Clock (Up to 200 MHz)
50kΩ
Figure 57. Balun-Coupled Differential Clock (Up to 625 MHz)
Figure 58. Differential PECL Sample Clock (Up to 625 MHz)
50Ω
0.1µF
50Ω
1nF
1nF
0.1µF
0.1µF
50kΩ
100Ω
ADT1–1WT, 1:1Z
Mini-Circuits
AD951x
PECL DRIVER
XFMR
0.1µF
240Ω
®
0.1µF
0.1µF
0.1µF
0.1µF
AD9510/AD9511/AD9512/
SCHOTTKY
SCHOTTKY
HSMS2822
HSMS2822
clock drivers offer excellent
DIODES:
DIODES:
240Ω
100Ω
0.1µF
0.1µF
AD9627-11
CLK+
CLK–
CLK+
AD9627-11
CLK–
CLK+
AD9627-11
CLK–
ADC
ADC
ADC