AD962711-105EBZ Analog Devices Inc, AD962711-105EBZ Datasheet - Page 44

• Manufacturer Part Number: AD962711-105EBZ
• Description: EVAL For 11bit 105 Dual 1.8V
• Manufacturer: Analog Devices Inc

Specifications of AD962711-105EBZ

• Number Of Adc's: 2
• Number Of Bits: 11
• Sampling Rate (per Second): 105M
• Data Interface: Serial
• Inputs Per Adc: 1 Differential
• Input Range: 1 ~ 2 Vpp
• Power (typ) @ Conditions: 600mW @ 105MSPS
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: AD962711
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9627-11
Addr
(Hex)
0x117
0x118
0x119
0x11A
0x11B
MEMORY MAP REGISTER DESCRIPTIONS
For additional information about functions controlled in
Register 0x00 to Register 0xFF, see Application Note AN-877,
Interfacing to High Speed ADCs via SPI.
Sync Control (Register 0x100)
Bit 7—Signal Monitor Sync Enable
Bit 7 enables the sync pulse from the external SYNC input to
the signal monitor block. The sync signal is passed when Bit 7
and Bit 0 are high. This is continuous sync mode.
Bits[6:3]—Reserved
Bit 2—Clock Divider Next Sync Only
If the master sync enable bit (Address 0x100, Bit 0) and the clock
divider sync enable bit (Address 0x100, Bit 1) are high, Bit 2
allows the clock divider to sync to the first sync pulse it receives
and to ignore the rest. The clock divider sync enable bit
(Address 0x100, Bit 1) resets after it syncs.
Bit 1—Clock Divider Sync Enable
Bit 1 gates the sync pulse to the clock divider. The sync signal is
passed when Bit 1 is high and Bit 0 is high. This is continuous
sync mode.
Bit 0—Master Sync Enable
Bit 0 must be high to enable any of the sync functions.
Fast Detect Control (Register 0x104)
Bits[7:4]—Reserved
Bits[3:1]—Fast Detect Mode Select
These bits set the mode of the fast detect output pins (see Table 14).
Register
Name
Signal Monitor
Result
Channel A
Register 1
(Global)
Signal Monitor
Result
Channel A
Register 2
(Global)
Signal Monitor
Result
Channel B
Register 0
(Global)
Signal Monitor
Result
Channel B
Register 1
(Global)
Signal Monitor
Result
Channel B
Register 2
(Global)
Bit 7
(MSB)
Open
Open
Bit 6
Open
Open
Bit 5
Open
Open
Signal Monitor Result Channel A[15:8]
Signal Monitor Result Channel B[15:8]
Signal Monitor Result Channel B[7:0]
Bit 4
Open
Open
Rev. A | Page 44 of 72
Bit 3
Bit 0—Fast Detect Enable
Bit 0 is used to enable the fast detect output pins. When the
fast detect output pins are disabled, the outputs go into a high
impedance state. In LVDS mode, when the outputs are inter-
leaved, the outputs go high-Z only if both channels are turned
off (power-down/standby/output disabled). If only one channel is
turned off (power-down/standby/output disabled), the fast detect
output pins repeat the data of the active channel.
Coarse Upper Threshold (Register 0x105)
Bits[7:3]—Reserved
Bits[2:0]—Coarse Upper Threshold
These bits set the level required to assert the coarse upper
threshold indication (see Table 18).
Fine Upper Threshold (Register 0x106 and Register 0x107)
Register 0x106, Bits[7:0]—Fine Upper Threshold[7:0]
Register 0x107, Bits[7:5]—Reserved
Register 0x107, Bits[4:0]—Fine Upper Threshold[12:8]
These registers provide the fine upper limit threshold. This 13-bit
value is compared to the 13-bit magnitude from the ADC block.
If the ADC magnitude exceeds this threshold value, the F_UT
flag is set.
Fine Lower Threshold (Register 0x108 and Register 0x109)
Register 0x108, Bits[7:0]—Fine Lower Threshold[7:0]
Register 0x109, Bits[7:5]—Reserved
Register 0x109, Bits[4:0]—Fine Lower Threshold[12:8]
These registers provide the fine lower limit threshold. This 13-bit
value is compared to the 13-bit magnitude from the ADC block.
If the ADC magnitude is less than this threshold value, the F_LT
flag is set.
Signal Monitor Result Channel B[19:16]
Signal Monitor Value Channel A[19:16]
Bit 2
Bit 1
Bit 0
(LSB)
Default
Value
(Hex)
Default
Notes/
Comments
Read only
Read only
Read only
Read only
Read only