AD962711-105EBZ Analog Devices Inc, AD962711-105EBZ Datasheet - Page 28

• Manufacturer Part Number: AD962711-105EBZ
• Description: EVAL For 11bit 105 Dual 1.8V
• Manufacturer: Analog Devices Inc

Specifications of AD962711-105EBZ

• Number Of Adc's: 2
• Number Of Bits: 11
• Sampling Rate (per Second): 105M
• Data Interface: Serial
• Inputs Per Adc: 1 Differential
• Input Range: 1 ~ 2 Vpp
• Power (typ) @ Conditions: 600mW @ 105MSPS
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: AD962711
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9627-11
The clock input should be treated as an analog signal in cases
where aperture jitter may affect the dynamic range of the
AD9627-11. Power supplies for clock drivers should be sepa-
rated from the ADC output driver supplies to avoid modulating
the clock signal with digital noise. Low jitter, crystal-controlled
oscillators make the best clock sources. If the clock is generated
from another type of source (by gating, dividing, or some other
method), it should be retimed by the original clock at the last step.
Refer to Application Note AN-501 and Application Note AN-756
(see www.analog.com) for more information about jitter perform-
ance as it relates to ADCs.
POWER DISSIPATION AND STANDBY MODE
As shown in Figure 63 and Figure 64, the power dissipated by
the AD9627-11 is proportional to its sample rate. In CMOS
output mode, the digital power dissipation is determined
primarily by the strength of the digital drivers and the load on
each output bit.
The maximum DRVDD current (I
where N is the number of output bits (24, in the case of the
AD9627-11, with the fast detect output pins disabled).
This maximum current occurs when every output bit switches
on every clock cycle, that is, a full-scale square wave at the
Nyquist frequency of f
is established by the average number of output bits switching,
which is determined by the sample rate and the characteristics
of the analog input signal.
Reducing the capacitive load presented to the output drivers can
minimize digital power consumption. The data in Figure 63 was
taken using the same operating conditions as those used for the
Typical Performance Characteristics, with a 5 pF load on each
output driver.
1.25
1.00
0.75
0.50
0.25
I
DRVDD
0
Figure 63. AD9627-11-150 Power and Current vs. Sample Rate
0
= V
25
DRVDD
TOTAL POWER
× C
CLK
50
SAMPLE RATE (MSPS)
LOAD
/2. In practice, the DRVDD current
I
DVDD
× f
75
CLK
I
AVDD
× N
DRVDD
100
) can be calculated as
I
DRVDD
125
150
0.5
0.4
0.3
0.2
0.1
0
Rev. A | Page 28 of 72
By asserting PDWN (either through the SPI port or by asserting
the PDWN pin high), the AD9627-11 is placed in power-down
mode. In this state, the ADC typically dissipates 2.5 mW. During
power-down, the output drivers are placed in a high impedance
state. Asserting the PDWN pin low returns the AD9627-11 to
its normal operating mode. Note that PDWN is referenced to
the digital output driver supply (DRVDD) and should not exceed
that supply voltage.
Low power dissipation in power-down mode is achieved by
shutting down the reference, reference buffer, biasing networks,
and clock. Internal capacitors are discharged when entering power-
down mode and then must be recharged when returning to normal
operation. As a result, wake-up time is related to the time spent
in power-down mode, and shorter power-down cycles result in
proportionally shorter wake-up times.
When using the SPI port interface, the user can place the ADC
in power-down mode or standby mode. Standby mode allows
the user to keep the internal reference circuitry powered when
faster wake-up times are required. See the Memory Map Register
Description section for more details.
DIGITAL OUTPUTS
The AD9627-11 output drivers can be configured to interface
with 1.8 V to 3.3 V CMOS logic families by matching DRVDD
to the digital supply of the interfaced logic. The AD9627-11 can
also be configured for LVDS outputs using a DRVDD supply
voltage of 1.8 V.
In CMOS output mode, the output drivers are sized to provide
sufficient output current to drive a wide variety of logic families.
However, large drive currents tend to cause current glitches on
the supplies that may affect converter performance.
Applications requiring the ADC to drive large capacitive loads
or large fanouts may require external buffers or latches.
1.00
0.75
0.50
0.25
0
Figure 64. AD9627-11-105 Power and Current vs. Sample Rate
0
I
DVDD
25
TOTAL POWER
I
AVDD
SAMPLE RATE (MSPS)
50
75
I
DRVDD
100
0.4
0.3
0.2
0.1
0