AD962711-105EBZ Analog Devices Inc, AD962711-105EBZ Datasheet - Page 35

• Manufacturer Part Number: AD962711-105EBZ
• Description: EVAL For 11bit 105 Dual 1.8V
• Manufacturer: Analog Devices Inc

Specifications of AD962711-105EBZ

• Number Of Adc's: 2
• Number Of Bits: 11
• Sampling Rate (per Second): 105M
• Data Interface: Serial
• Inputs Per Adc: 1 Differential
• Input Range: 1 ~ 2 Vpp
• Power (typ) @ Conditions: 600mW @ 105MSPS
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: AD962711
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DC Correction Bandwidth
The dc correction circuit is a high-pass filter with a programmable
bandwidth (ranging between 0.15 Hz and 1.2 kHz at 125 MSPS).
The bandwidth is controlled by writing the 4-bit dc correction
register located at Register 0x10C, Bits[5:2].
The following equation can be used to compute the bandwidth
value for the dc correction circuit:
where:
k is the 4-bit value programmed in Register 0x10C, Bits[5:2]
(values between 0 and 13 are valid for k; programming 14 or 15
provides the same result as programming 13).
f
DC Correction Readback
The current dc correction value can be read back in Register 0x10D
and Register 0x10E for Channel A and Register 0x10F and
Register 0x110 for Channel B. The dc correction value is an 11-bit
value that can span the entire input range of the ADC.
DC Correction Freeze
Setting Bit 6 of Register 0x10C freezes the dc correction at its
current state and continues to use the last updated value as the
dc correction value. Clearing this bit restarts dc correction and
adds the currently calculated value to the data.
DC Correction Enable Bits
Setting Bit 0 of Register 0x10C enables dc correction for use in
the signal monitor calculations. The calculated dc correction
value can be added to the output data signal path by setting Bit 1
of Register 0x10C.
SMI SCLK
SMI SDFS
CLK
SMI SDO
SMI SCLK
SMI SDFS
SMI SDO
is the AD9627-11 ADC sample rate in hertz (Hz).
DC
_
Corr
_
BW
MSB
=
20 CYCLES
MSB
2
RMS/MS CH A
−
k
−
20 CYCLES
14
RMS/MS CH A
×
2
f
LSB
Figure 69. Signal Monitor SPORT Output Timing (RMS, Peak, and Threshold Enabled)
CLK
×
π
Figure 70. Signal Monitor SPORT Output Timing (RMS and Threshold Enabled)
16 CYCLES
LSB
PK CH A
16 CYCLES
16 CYCLES
THR CH A
THR CH A
Rev. A | Page 35 of 72
MSB
MSB
20 CYCLES
20 CYCLES
RMS/MS CH B
RMS/MS CH B LSB
SIGNAL MONITOR SPORT OUTPUT
The SPORT is a serial interface with three output pins:
SMI SCLK (SPORT clock), SMI SDFS (SPORT frame sync) and
SMI SDO (SPORT data output). The SPORT is the master and
drives all three SPORT output pins on the chip.
SMI SCLK
The data and frame sync are driven on the positive edge of the SMI
SCLK. The SMI SCLK has three possible baud rates: 1/2, 1/4, or 1/8
the ADC clock rate, based on the SPORT controls. The SMI SCLK
can also be gated off when not sending any data by using the
SPORT SMI SCLK sleep bit. Using this bit to disable the SMI SCLK
when it is not needed can reduce any coupling errors back into the
signal path, if these prove to be a problem in the system. Doing so,
however, has the disadvantage of spreading the frequency content
of the clock. If desired, the SMI SCLK can be left running to ease
frequency planning.
SMI SDFS
The SMI SDFS is the serial data frame sync, and it defines the
start of a frame. One SPORT frame includes data from both
datapaths. The data from Datapath A is sent just after the frame
sync, followed by data from Datapath B.
SMI SDO
The SMI SDO is the serial data output of the block. The data
is sent MSB first on the next positive edge after the SMI SDFS.
Each data output block includes one or more rms magnitude, peak
level, and threshold crossing values from each datapath in the
stated order. If enabled, the data is sent, rms first, followed by peak
and threshold, as shown in Figure 69.
GATED, BASED ON CONTROL
LSB
GATED, BASED ON CONTROL
16 CYCLES
PK CH B
16 CYCLES
THR CH B
16 CYCLES
THR CH B
RMS/MS CH A
AD9627-11
RMS/MS CH A