AD962711-105EBZ Analog Devices Inc, AD962711-105EBZ Datasheet - Page 29

• Manufacturer Part Number: AD962711-105EBZ
• Description: EVAL For 11bit 105 Dual 1.8V
• Manufacturer: Analog Devices Inc

Specifications of AD962711-105EBZ

• Number Of Adc's: 2
• Number Of Bits: 11
• Sampling Rate (per Second): 105M
• Data Interface: Serial
• Inputs Per Adc: 1 Differential
• Input Range: 1 ~ 2 Vpp
• Power (typ) @ Conditions: 600mW @ 105MSPS
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: AD962711
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The output data format can be selected for either offset binary
or twos complement by setting the SCLK/DFS pin when operating
in the external pin mode (see Table 12).
As detailed in Application Note AN-877, Interfacing to High
Speed ADCs via SPI, the data format can be selected for offset
binary, twos complement, or gray code when using the SPI control.
Table 12. SCLK/DFS Mode Selection (External Pin Mode)
Voltage at Pin
AGND
AVDD
Digital Output Enable Function (OEB)
The AD9627-11 has a flexible three-state ability for the digital
output pins. The three-state mode is enabled using the SMI
SDO/OEB pin or through the SPI interface. If the SMI SDO/OEB
pin is low, the output data drivers are enabled. If the SMI SDO/OEB
pin is high, the output data drivers are placed in a high impedance
state. This OEB function is not intended for rapid access to the
data bus. Note that OEB is referenced to the digital output driver
supply (DRVDD) and should not exceed that supply voltage.
Table 13. Output Data Format
Input (V)
VIN+ − VIN−
VIN+ − VIN−
VIN+ − VIN−
VIN+ − VIN−
VIN+ − VIN−
SCLK/DFS
Offset binary (default)
Twos complement
Condition (V)
< −VREF − 0.5 LSB
= −VREF
= 0
= +VREF − 1.0 LSB
> +VREF − 0.5 LSB
SDIO/DCS
DCS disabled
DCS enabled (default)
Offset Binary Output Mode
000 0000 0000
000 0000 0000
100 0000 0000
111 1111 1111
111 1111 1111
Rev. A | Page 29 of 72
When using the SPI interface, the data and fast detect outputs
of each channel can be independently three-stated by using the
output enable bar bit in Register 0x14.
TIMING
The AD9627-11 provides latched data with a pipeline delay of
12 clock cycles. Data outputs are available one propagation
delay (t
The length of the output data lines and loads placed on them
should be minimized to reduce transients within the AD9627-11.
These transients can degrade converter dynamic performance.
The lowest typical conversion rate of the AD9627-11 is 10 MSPS.
At clock rates below 10 MSPS, dynamic performance can degrade.
Data Clock Output (DCO)
The AD9627-11 provides two data clock output (DCO) signals
intended for capturing the data in an external register. The data
outputs are valid on the rising edge of DCO, unless the DCO clock
polarity has been changed via the SPI. See Figure 2 and Figure 3
for a graphical timing description.
PD
) after the rising edge of the clock signal.
Twos Complement Mode
100 0000 0000
100 0000 0000
000 0000 0000
011 1111 1111
011 1111 1111
AD9627-11
OR
1
0
0
0
1