AD962711-105EBZ Analog Devices Inc, AD962711-105EBZ Datasheet - Page 30

• Manufacturer Part Number: AD962711-105EBZ
• Description: EVAL For 11bit 105 Dual 1.8V
• Manufacturer: Analog Devices Inc

Specifications of AD962711-105EBZ

• Number Of Adc's: 2
• Number Of Bits: 11
• Sampling Rate (per Second): 105M
• Data Interface: Serial
• Inputs Per Adc: 1 Differential
• Input Range: 1 ~ 2 Vpp
• Power (typ) @ Conditions: 600mW @ 105MSPS
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: AD962711
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9627-11
ADC OVERRANGE AND GAIN CONTROL
In receiver applications, it is desirable to have a mechanism to
reliably determine when the converter is about to be clipped.
The standard overflow indicator provides after-the-fact infor-
mation on the state of the analog input that is of limited usefulness.
Therefore, it is helpful to have a programmable threshold below
full scale that allows time to reduce the gain before the clip
actually occurs. In addition, because input signals can have
significant slew rates, latency of this function is of major concern.
Highly pipelined converters can have significant latency. A good
compromise is to use the output bits from the first stage of the
ADC for this function. Latency for these output bits is very low,
and overall resolution is not highly significant. Peak input signals
are typically between full scale and 6 dB to 10 dB below full
scale. A 3-bit or 4-bit output provides adequate range and
resolution for this function.
Using the SPI port, the user can provide a threshold above which
an overrange output is active. As long as the signal is below that
threshold, the output should remain low. The fast detect outputs
can also be programmed via the SPI port so that one of the pins
functions as a traditional overrange pin for customers who
currently use this feature. In this mode, all 11 bits of the converter
are examined in the traditional manner, and the output is high for
the condition normally defined as overflow. In either mode, the
magnitude of the data is considered in the calculation of the
condition (but the sign of the data is not considered). The
threshold detection responds identically to positive and negative
signals outside the desired range (magnitude).
FAST DETECT OVERVIEW
The AD9627-11 contains circuitry to facilitate fast overrange detec-
tion, allowing very flexible external gain control implementations.
Each ADC has four fast detect (FD) output pins that are used to
output information about the current state of the ADC input
level. The function of these pins is programmable via the fast detect
mode select bits and the fast detect enable bits in Register 0x104,
allowing range information to be output from several points in
the internal datapath. These output pins can also be set up to
indicate the presence of overrange or underrange conditions,
according to programmable threshold levels. Table 14 shows the
six configurations available for the fast detect pins.
Rev. A | Page 30 of 72
Table 14. Fast Detect Mode Select Bits Settings
Fast Detect
Mode Select Bits
(Register 0x104[3:1])
000
001
010
011
100
101
1
2
ADC FAST MAGNITUDE
When the fast detect output pins are configured to output the ADC
fast magnitude (that is, when the fast detect mode select bits are
set to 0b000), the information presented is the ADC level from
an early converter stage with a latency of only two clock cycles
(when in CMOS output mode). Using the fast detect output pins in
this configuration provides the earliest possible level indication
information. Because this information is provided early in the
datapath, there is significant uncertainty in the level indicated.
The nominal levels, along with the uncertainty indicated by the
ADC fast magnitude, are shown in Table 15.
Table 15. ADC Fast Magnitude Nominal Levels
with Fast Detect Mode Select Bits = 000
ADC Fast
Magnitude on
FD[3:0] Pins
0000
0001
0010
0011
0100
0101
0110
0111
1000
The fast detect pins are FD0A/FD0B to FD9A/FD9B for the CMOS mode
configuration and FD0+/FD0− to FD9+/FD9− for the LVDS mode
configuration.
See the ADC Overrange (OR) and Gain Switching sections for more
information about OR, C_UT, F_UT, F_LT, IG, and DG.
Nominal Input
Magnitude
Below FS (dB)
<−24
−24 to −14.5
−14.5 to −10
−10 to −7
−7 to −5
−5 to −3.25
−3.25 to −1.8
−1.8 to −0.56
−0.56 to 0
FD[3]
OR
OR
ADC fast magnitude
ADC fast magnitude
Fast Detect (FD) Pins of Each ADC
(see Table 17)
(see Table 17)
ADC fast magnitude
Information Presented on
(see Table 16)
FD[2]
C_UT
F_UT
ADC fast magnitude
(see Table 15)
Nominal Input
Magnitude
Uncertainty (dB)
Minimum to −18.07
−18.07 to −8.52
−12.04 to −6.02
−6.02 to −2.5
−4.08 to −1.16
−2.5 to FS
−1.16 to 0
−30.14 to −12.04
−8.52 to −4.08
FD[1]
OR
C_UT
F_UT
IG
FD[0]
OR
F_LT
F_LT
F_LT
DG
1, 2