AD962711-105EBZ Analog Devices Inc, AD962711-105EBZ Datasheet - Page 27

• Manufacturer Part Number: AD962711-105EBZ
• Description: EVAL For 11bit 105 Dual 1.8V
• Manufacturer: Analog Devices Inc

Specifications of AD962711-105EBZ

• Number Of Adc's: 2
• Number Of Bits: 11
• Sampling Rate (per Second): 105M
• Data Interface: Serial
• Inputs Per Adc: 1 Differential
• Input Range: 1 ~ 2 Vpp
• Power (typ) @ Conditions: 600mW @ 105MSPS
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: AD962711
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

CLOCK
In some applications, it may be acceptable to drive the sample
clock inputs with a single-ended CMOS signal. In such applica-
tions, the CLK+ pin should be driven directly from a CMOS gate,
and the CLK− pin should be bypassed to ground with a 0.1 μF
capacitor in parallel with a 39 kΩ resistor (see Figure 60).
CLK+ can be driven directly from a CMOS gate. Although the
CLK+ input circuit supply is AVDD (1.8 V), this input is designed
to withstand input voltages of up to 3.6 V, making the selection
of the drive logic voltage very flexible.
CLOCK
CLOCK
Input Clock Divider
The AD9627-11 contains an input clock divider with the ability
to divide the input clock by integer values between 1 and 8. If a
divide ratio other than 1 is selected, the duty cycle stabilizer is
automatically enabled.
The AD9627-11 clock divider can be synchronized using the
external SYNC input. Bit 1 and Bit 2 of Register 0x100 allow the
clock divider to be resynchronized on every SYNC signal or only
on the first SYNC signal after the register is written. A valid
SYNC causes the clock divider to reset to its initial state. This
synchronization feature allows multiple parts to have their clock
dividers aligned to guarantee simultaneous input sampling.
CLOCK
INPUT
INPUT
INPUT
INPUT
Figure 60. Single-Ended 1.8 V CMOS Sample Clock (Up to 150 MSPS)
Figure 61. Single-Ended 3.3 V CMOS Sample Clock (Up to 150 MSPS)
50kΩ
1
Figure 59. Differential LVDS Sample Clock (Up to 625 MHz)
50Ω RESISTOR IS OPTIONAL.
50Ω
50Ω
1
50Ω RESISTOR IS OPTIONAL.
0.1µF
0.1µF
1
1
0.1µF
0.1µF
50kΩ
V
V
CC
CC
1kΩ
1kΩ
1kΩ
1kΩ
AD951x
LVDS DRIVER
AD951x
CMOS DRIVER
AD951x
CMOS DRIVER
0.1µF
OPTIONAL
OPTIONAL
100Ω
100Ω
100Ω
39kΩ
0.1µF
0.1µF
0.1µF
0.1µF
0.1µF
AD9627-11
CLK+
CLK–
AD9627-11
AD9627-11
CLK+
CLK–
CLK+
CLK–
ADC
ADC
ADC
Rev. A | Page 27 of 72
Clock Duty Cycle
Typical high speed ADCs use both clock edges to generate
a variety of internal timing signals and, as a result, may be
sensitive to clock duty cycle. Commonly, a ±5% tolerance is
required on the clock duty cycle to maintain dynamic
performance characteristics.
The AD9627-11 contains a duty cycle stabilizer (DCS) that retimes
the nonsampling (falling) edge, providing an internal clock signal
with a nominal 50% duty cycle. This allows the user to provide
a wide range of clock input duty cycles without affecting the
performance of the AD9627-11. Noise and distortion performance
are nearly flat for a wide range of duty cycles with the DCS on,
as shown in Figure 43.
Jitter in the rising edge of the input is still of paramount concern
and is not easily reduced by the internal stabilization circuit.
The duty cycle control loop does not function for clock rates
less than 20 MHz nominally. The loop has a time constant
associated with it that must be considered where the clock rate
can change dynamically. A wait time of 1.5 μs to 5 μs is required
after a dynamic clock frequency increase or decrease before the
DCS loop is relocked to the input signal. During the time period
that the loop is not locked, the DCS loop is bypassed, and internal
device timing is dependent on the duty cycle of the input clock
signal. In such applications, it may be appropriate to disable the
duty cycle stabilizer. In all other applications, enabling the DCS
circuit is recommended to maximize ac performance.
Jitter Considerations
High speed, high resolution ADCs are sensitive to the quality
of the clock input. The degradation in SNR from the low
frequency SNR (SNR
to jitter (t
In the equation, the rms aperture jitter represents the clock input
jitter specification. IF undersampling applications are particularly
sensitive to jitter, as illustrated in Figure 62.
SNR
70
65
60
55
50
45
HF
JRMS
1
= −10 log[(2π × f
MEASURED
) can be calculated by
Figure 62. SNR vs. Input Frequency and Jitter
LF
) at a given input frequency (f
INPUT FREQUENCY (MHz)
10
INPUT
× t
JRMS
)
100
2
+ 10
AD9627-11
(
−
SNR
0.05ps
0.20ps
0.5ps
1.0ps
1.50ps
2.00ps
2.50ps
3.00ps
LF
INPUT
/
10
)
1000
]
) due