AD962711-105EBZ Analog Devices Inc, AD962711-105EBZ Datasheet - Page 43

• Manufacturer Part Number: AD962711-105EBZ
• Description: EVAL For 11bit 105 Dual 1.8V
• Manufacturer: Analog Devices Inc

Specifications of AD962711-105EBZ

• Number Of Adc's: 2
• Number Of Bits: 11
• Sampling Rate (per Second): 105M
• Data Interface: Serial
• Inputs Per Adc: 1 Differential
• Input Range: 1 ~ 2 Vpp
• Power (typ) @ Conditions: 600mW @ 105MSPS
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: AD962711
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Addr
(Hex)
0x109
0x10A
0x10B
0x10C
0x10D
0x10E
0x10F
0x110
0x111
0x112
0x113
0x114
0x115
0x116
Register
Name
Fine Lower
Threshold
Register 1
(Local)
Increase Gain
Dwell Time
Register 0
(Local)
Increase Gain
Dwell Time
Register 1
(Local)
Signal Monitor
DC
Correction
Control
(Global)
Signal Monitor
DC Value
Channel A
Register 0
(Global)
Signal Monitor
DC Value
Channel A
Register 1
(Global)
Signal Monitor
DC Value
Channel B
Register 0
(Global)
Signal Monitor
DC Value
Channel B
Register 1
(Global)
Signal Monitor
SPORT Control
(Global)
Signal Monitor
Control
(Global)
Signal Monitor
Period
Register 0
(Global)
Signal Monitor
Period
Register 1
(Global)
Signal Monitor
Period
Register 2
(Global)
Signal Monitor
Result
Channel A
Register 0
(Global)
Bit 7
(MSB)
Open
Open
Open
Open
Open
Complex
power
calculation
mode
enable
Bit 6
Open
DC
correction
freeze
Open
Open
RMS/MS
magnitude
output
enable
Open
Bit 5
Open
Peak
detector
output
enable
Open
Signal Monitor Result Channel A[7:0]
DC Correction Bandwidth[3:0]
Increase Gain Dwell Time[15:8]
Increase Gain Dwell Time[7:0]
Signal Monitor Period[23:16]
Signal Monitor Period[15:8]
Signal Monitor Period[7:0]
Bit 4
DC Value Channel A[7:0]
Threshold
crossing
output
enable
Open
DC Value Channel B[7:0]
Rev. A | Page 43 of 72
Bit 3
Signal
monitor
rms/ms
select
0 = rms
1 = ms
DC Value Channel A[13:8]
DC Value Channel B[13:8]
01 = divide by 2
10 = divide by 4
11 = divide by 8
00 = undefined
SCLK divide
SPORT SMI
Fine Lower Threshold[12:8]
Bit 2
Signal monitor mode
00 = rms/ms magnitude
01 = peak detector
10 = threshold crossing
11 = threshold crossing
Bit 1
DC
correction
for signal
path
enable
SPORT
SMI SCLK
sleep
Bit 0
(LSB)
DC
correction
for signal
monitor
enable
Signal
monitor
SPORT
output enable
Signal
monitor
enable
0x00
0x00
0x00
Default
Value
(Hex)
0x00
0x00
0x04
0x00
0x40
0x00
AD9627-11
Default
Notes/
Comments
In ADC clock
cycles
In ADC clock
cycles
Read only
Read only
Read only
Read only
In ADC clock
cycles
In ADC clock
cycles
In ADC clock
cycles
Read only