AD962711-105EBZ Analog Devices Inc, AD962711-105EBZ Datasheet - Page 42

• Manufacturer Part Number: AD962711-105EBZ
• Description: EVAL For 11bit 105 Dual 1.8V
• Manufacturer: Analog Devices Inc

Specifications of AD962711-105EBZ

• Number Of Adc's: 2
• Number Of Bits: 11
• Sampling Rate (per Second): 105M
• Data Interface: Serial
• Inputs Per Adc: 1 Differential
• Input Range: 1 ~ 2 Vpp
• Power (typ) @ Conditions: 600mW @ 105MSPS
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: AD962711
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9627-11
Addr
(Hex)
0x0E
0x10
0x14
0x16
0x17
0x18
0x24
0x25
Digital Feature Control
0x100
0x104
0x105
0x106
0x107
0x108
Register
Name
BIST Enable
(Local)
Offset Adjust
(Local)
Output Mode
Clock Phase
Control
(Global)
DCO Output
Delay
(Global)
VREF Select
(Global)
BIST
Signature LSB
(Local)
BIST
Signature
MSB (Local)
Sync Control
(Global)
Fast Detect
Control
(Local)
Coarse Upper
Threshold
(Local)
Fine Upper
Threshold
Register 0
(Local)
Fine Upper
Threshold
Register 1
(Local)
Fine Lower
Threshold
Register 0
(Local)
Bit 7
(MSB)
Open
Open
Drive
strength
0 V to 3.3 V
CMOS or
ANSI
LVDS;
1 V to 1.8 V
CMOS or
reduced
LVDS
(global)
Invert
DCO clock
Open
Signal
monitor
sync
enable
Open
Open
Open
Reference voltage
selection
00 = 1.25 V p-p
01 = 1.5 V p-p
10 = 1.75 V p-p
11 = 2.0 V p-p (default)
Bit 6
Open
Open
Output
type
0 = CMOS
1 = LVDS
(global)
Open
Open
Open
Open
Open
Open
Bit 5
Open
Open
Open
Open
Open
Open
Open
Open
Open
Fine Upper Threshold[7:0]
Fine Lower Threshold[7:0]
Bit 4
Open
Output
enable bar
(local)
Open
Open
Open
Open
Open
BIST Signature[15:8]
BIST Signature[7:0]
Rev. A | Page 42 of 72
Offset adjust in LSBs from +31 to −32
Bit 3
Open
(twos complement format)
Open
Open
Open
Open
Open
(delay = 2500 ps × register value/31)
Fast Detect Mode Select[2:0]
Fine Upper Threshold[12:8]
DCO clock delay
00000 = 0 ps
00001 = 81 ps
00010 = 161 ps
…
11110 = 2419 ps
11111 = 2500 ps
Bit 2
Reset BIST
sequence
Output
invert
(local)
Open
Clock
divider
next sync
only
Input clock divider phase adjust
Coarse Upper Threshold[2:0]
000 = no delay
001 = 1 input clock cycle
010 = 2 input clock cycles
011 = 3 input clock cycles
100 = 4 input clock cycles
101 = 5 input clock cycles
110 = 6 input clock cycles
111 = 7 input clock cycles
Bit 1
Open
Open
Clock
divider
sync
enable
00 = offset binary
01 = twos complement
01 = gray code
11 = offset binary
(local)
Bit 0
(LSB)
BIST enable
Open
Master
sync
enable
Fast detect
enable
Default
Value
(Hex)
0x00
0x00
0x00
0x00
0x00
0xC0
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
Default
Notes/
Comments
Configures the
outputs and
the format of
the data
Allows
selection of
clock delays
into the input
clock divider
Read only
Read only