ADSP-21160MKBZ-80 Analog Devices Inc, ADSP-21160MKBZ-80 Datasheet - Page 15

• Manufacturer Part Number: ADSP-21160MKBZ-80
• Description: 32bit SHARC W/SIMD Capability
• Manufacturer: Analog Devices Inc
• Series: SHARC®r
• Type: Floating Pointr

Specifications of ADSP-21160MKBZ-80

• Interface: Host Interface, Link Port, Serial Port
• Clock Rate: 80MHz
• Non-volatile Memory: External
• On-chip Ram: 512kB
• Voltage - I/o: 3.30V
• Voltage - Core: 2.50V
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 400-BGA
• Device Core Size: 32b
• Architecture: Enhanced Harvard
• Format: Floating Point
• Clock Freq (max): 80MHz
• Mips: 80
• Device Input Clock Speed: 80MHz
• Ram Size: 512KB
• Operating Supply Voltage (typ): 2.5/3.3V
• Operating Supply Voltage (min): 2.37/3.13V
• Operating Supply Voltage (max): 2.63/3.47V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 400
• Package Type: BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Timing Specifications
The ADSP-21160M’s internal clock switches at higher fre-
quencies than the system input clock (CLKIN). To generate
the internal clock, the DSP uses an internal phase-locked
loop (PLL). This PLL-based clocking minimizes the skew
between the system clock (CLKIN) signal and the DSP’s
internal clock (the clock source for the external port logic
and I/O pads).
The ADSP-21160M’s internal clock (a multiple of CLKIN)
provides the clock signal for timing internal memory,
processor core, link ports, serial ports, and external port (as
required for read/write strobes in asynchronous access
mode). During reset, program the ratio between the DSP’s
internal clock frequency and external (CLKIN) clock
frequency with the CLK_CFG3–0 pins. Even though the
internal clock is the clock source for the external port, the
external port clock always switches at the CLKIN fre-
quency. To determine switching frequencies for the serial
and link ports, divide down the internal clock, using the
programmable divider control of each port (TDIVx/RDIVx
for the serial ports and LxCLKD1–0 for the link ports).
Note the following definitions of various clock periods that
are a function of CLKIN and the appropriate ratio control:
• t
• t
• t
Where:
• LCLK = Link Port Clock
• SCLK = Serial Port Clock
• t
• t
• t
• t
• CR = Core/CLKIN Ratio (2, 3, or 4:1,
• LR = Link Port/Core Clock Ratio (1, 2, 3, or 4:1,
• SR = Serial Port/Core Clock Ratio (wide range,
Use the exact timing information given. Do not attempt to
derive parameters from the addition or subtraction of
others. While addition or subtraction would yield meaning-
ful results for an individual device, the values given in this
data sheet reflect statistical variations and worst cases. Con-
sequently, it is not meaningful to add parameters to derive
longer times.
See
levels.
REV. 0
determined by CLK_CFG3–0 at reset)
determined by LxCLKD)
determined by CLKDIV)
CCLK
LCLK
SCLK
CK
CCLK
LCLK
SCLK
Figure 32
= CLKIN Clock Period
= (t
= Serial Port Clock Period
= (t
= (t
= (Processor) Core Clock Period
= Link Port Clock Period
CCLK
CCLK
CK
) / CR
)
)
under Test Conditions for voltage reference
LR
SR
–15–
Switching Characteristics specify how the processor
changes its signals. Circuitry external to the processor must
be designed for compatibility with these signal characteris-
tics. Switching characteristics describe what the processor
will do in a given circumstance. Use switching characteris-
tics to ensure that any timing requirement of a device
connected to the processor (such as memory) is satisfied.
Timing Requirements apply to signals that are controlled
by circuitry external to the processor, such as the data input
for a read operation. Timing requirements guarantee that
the processor operates correctly with other devices.
ADSP-21160M