ADSP-21160MKBZ-80 Analog Devices Inc, ADSP-21160MKBZ-80 Datasheet - Page 32

• Manufacturer Part Number: ADSP-21160MKBZ-80
• Description: 32bit SHARC W/SIMD Capability
• Manufacturer: Analog Devices Inc
• Series: SHARC®r
• Type: Floating Pointr

Specifications of ADSP-21160MKBZ-80

• Interface: Host Interface, Link Port, Serial Port
• Clock Rate: 80MHz
• Non-volatile Memory: External
• On-chip Ram: 512kB
• Voltage - I/o: 3.30V
• Voltage - Core: 2.50V
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 400-BGA
• Device Core Size: 32b
• Architecture: Enhanced Harvard
• Format: Floating Point
• Clock Freq (max): 80MHz
• Mips: 80
• Device Input Clock Speed: 80MHz
• Ram Size: 512KB
• Operating Supply Voltage (typ): 2.5/3.3V
• Operating Supply Voltage (min): 2.37/3.13V
• Operating Supply Voltage (max): 2.63/3.47V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 400
• Package Type: BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

ADSP-21160M
DMA Handshake
These specifications describe the three DMA handshake
modes. In all three modes DMAR is used to initiate trans-
fers. For handshake mode, DMAG controls the latching or
enabling of data externally. For external handshake mode,
the data transfer is controlled by the ADDR31–0, RDx,
WRx, PAGE, MS3–0, ACK, and DMAG signals. For Paced
Table 17. DMA Handshake
1
2
3
4
5
6
7
Only required for recognition in the current cycle.
Maximum throughput using DMARx/DMAGx handshaking equals t
applies to non-synchronous access mode only.
t
the write, the data can be driven t
Use t
t
t
See
This parameter applies for synchronous access mode only.
Parameter
Timing Requirements:
t
t
t
t
t
t
t
Switching Characteristics:
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
W = (number of wait states specified in WAIT register)
HI = t
SDATDGL
VDATDGH
VDATDGH
SDRC
WDR
SDATDGL
HDATIDG
DATDRH
DMARLL
DMARH
DDGL
WDGH
WDGL
HDGC
VDATDGH
DATRDGH
DGWRL
DGWRH
DGWRR
DGRDL
DRDGH
DGRDR
DGWR
DADGH
DDGHA
Example System Hold Time Calculation on page 44
DMARLL
CK
is the data setup requirement if DMARx is not being used to hold off completion of a write. Otherwise, if DMARx low holds off completion of
is valid if DMARx is not being used to hold off completion of a read. If DMARx is used to prolong the read, then
= t
(if data bus idle cycle occurs, as specified in WAIT register; otherwise HI = 0).
CK
if DMARx transitions synchronous with CLKIN. Otherwise, use t
– .25t
CCLK
DMARx Setup Before CLKIN
DMARx Width Low (Nonsynchronous)
Data Setup After DMAGx Low
Data Hold After DMAGx High
Data Valid After DMARx High
DMARx Low Edge to Low Edge
DMARx Width High
DMAGx Low Delay After CLKIN
DMAGx High Width
DMAGx Low Width
DMAGx High Delay After CLKIN
Data Valid Before DMAGx High
Data Disable After DMAGx High
WRx Low Before DMAGx Low
DMAGx Low Before WRx High
WRx High Before DMAGx High
RDx Low Before DMAGx Low
RDx Low Before DMAGx High
RDx High Before DMAGx High
DMAGx High to WRx, RDx, DMAGx
Low
Address/Select Valid to DMAGx High
Address/Select Hold after DMAGx High
– 8 + (n × t
DATDRH
CK
) where n equals the number of extra cycles that the access is prolonged.
after DMARx is brought high.
2
for calculation of hold times given capacitive and dc loads.
1
3
3
7
4
5
7
6
WDR
+ t
2
–32–
t
DMARH
CK
.
Master mode, the data transfer is controlled by ADDR31–0,
RDx, WRx, MS3–0, and ACK (not DMAG). For Paced
Master mode, the Memory Read-Bus Master, Memory
Write-Bus Master, and Synchronous Read/Write-Bus
Master timing specifications for ADDR31–0, RDx, WRx,
MS3–0, PAGE, DATA63–0, and ACK also apply.
WDR
Min
3
t
2
t
t
0.25t
0.5t
t
t
t
0.25t
–1.5
t
–1.5
–1.5
t
–1.5
0.5t
18
1
CCLK
CK
CCLK
CK
CK
CK
CK
CK
= (t
– 0.5t
– 0.25t
– 0.25t
– 0.5t
– 0.5t
and t
CCLK
CCLK
+4.5
+4.5
CCLK
CCLK
CCLK
DMARH
– 1+HI
– 2+HI
CCLK
CCLK
CCLK
+4.5) + (t
+1
– 3
CCLK
CCLK
.
–2+W
– 1
– 2 +W
+1.5
– 8
CCLK
+4.5)=34ns (29.4 MHz). This throughput limit
Max
0.75t
t
0.25t
t
t
0.25t
2
2
2
2
CK
CK
CK
+10
– 0.25t
– 0.25t
CK
CCLK
CCLK
– 7
+9
+1.5
CCLK
CCLK
+9
+5
REV. 0
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns