ADSP-21160MKBZ-80 Analog Devices Inc, ADSP-21160MKBZ-80 Datasheet - Page 3

• Manufacturer Part Number: ADSP-21160MKBZ-80
• Description: 32bit SHARC W/SIMD Capability
• Manufacturer: Analog Devices Inc
• Series: SHARC®r
• Type: Floating Pointr

Specifications of ADSP-21160MKBZ-80

• Interface: Host Interface, Link Port, Serial Port
• Clock Rate: 80MHz
• Non-volatile Memory: External
• On-chip Ram: 512kB
• Voltage - I/o: 3.30V
• Voltage - Core: 2.50V
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 400-BGA
• Device Core Size: 32b
• Architecture: Enhanced Harvard
• Format: Floating Point
• Clock Freq (max): 80MHz
• Mips: 80
• Device Input Clock Speed: 80MHz
• Ram Size: 512KB
• Operating Supply Voltage (typ): 2.5/3.3V
• Operating Supply Voltage (min): 2.37/3.13V
• Operating Supply Voltage (max): 2.63/3.47V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 400
• Package Type: BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

The functional block diagram
diagram of the ADSP-21160M, illustrating the following
architectural features:
• Two processing elements, each made up of an ALU, Mul-
• Data Address Generators (DAG1, DAG2)
• Program sequencer with instruction cache
• PM and DM buses capable of supporting four 32-bit data
• Interval timer
• On-Chip SRAM (4 Mbit)
• External port that supports:
• DMA controller
• Serial ports and link ports
• JTAG test access port
Figure 1
processing system appears in
Figure 1. Single-Processor System
REV. 0
tiplier, Shifter, and Data Register File
transfers between memory and the core every core
processor cycle
• Interfacing to off-chip memory peripherals
• Glueless multiprocessing support for six
• Host port
ADSP-21160M SHARCs
shows a typical single-processor system. A multi-
Figure
on page 1
4.
shows a block
–3–
ADSP-21160M Family Core Architecture
The ADSP-21160M includes the following archi-
tectural features of the ADSP-2116x family core. The
ADSP-21160M is code compatible at the assembly level
with the ADSP-21060, ADSP-21061, and ADSP-21062.
SIMD Computational Engine
The ADSP-21160M contains two computational process-
ing elements that operate as a Single Instruction Multiple
Data (SIMD) engine. The processing elements are referred
to as PEX and PEY, and each contains an ALU, multiplier,
shifter, and register file. PEX is always active, and PEY may
be enabled by setting the PEYEN mode bit in the MODE1
register. When this mode is enabled, the same instruction
is executed in both processing elements, but each processing
element operates on different data. This architecture is
efficient at executing math-intensive DSP algorithms.
Entering SIMD mode also has an effect on the way data is
transferred between memory and the processing elements.
When in SIMD mode, twice the data bandwidth is required
to sustain computational operation in the processing
elements. Because of this requirement, entering SIMD
mode also doubles the bandwidth between memory and the
processing elements. When using the DAGs to transfer data
in SIMD mode, two data values are transferred with each
access of memory or the register file.
Independent, Parallel Computation Units
Within each processing element is a set of computational
units. The computational units consist of an arith-
metic/logic unit (ALU), multiplier, and shifter. These units
perform single-cycle instructions. The three units within
each processing element are arranged in parallel, maximiz-
ing computational throughput. Single multifunction
instructions execute parallel ALU and multiplier opera-
tions. In SIMD mode, the parallel ALU and multiplier
operations occur in both processing elements. These com-
putation units support IEEE 32-bit single-precision
floating-point, 40-bit extended precision floating-point,
and 32-bit fixed-point data formats.
Data Register File
A general-purpose data register file is contained in each
processing element. The register files transfer data between
the computation units and the data buses, and store inter-
mediate results. These 10-port, 32-register (16 primary, 16
secondary) register files, combined with the ADSP-2116x
enhanced Harvard architecture, allow unconstrained data
flow between computation units and internal memory. The
registers in PEX are referred to as R0–R15 and in PEY
as S0–S15.
Single-Cycle Fetch of Instruction and Four Operands
The ADSP-21160M features an enhanced Harvard archi-
tecture in which the data memory (DM) bus transfers data,
and the program memory (PM) bus transfers both instruc-
tions and data (see the functional block diagram
ADSP-21160M
on page
1).