ADSP-21160MKBZ-80 Analog Devices Inc, ADSP-21160MKBZ-80 Datasheet - Page 43

• Manufacturer Part Number: ADSP-21160MKBZ-80
• Description: 32bit SHARC W/SIMD Capability
• Manufacturer: Analog Devices Inc
• Series: SHARC®r
• Type: Floating Pointr

Specifications of ADSP-21160MKBZ-80

• Interface: Host Interface, Link Port, Serial Port
• Clock Rate: 80MHz
• Non-volatile Memory: External
• On-chip Ram: 512kB
• Voltage - I/o: 3.30V
• Voltage - Core: 2.50V
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 400-BGA
• Device Core Size: 32b
• Architecture: Enhanced Harvard
• Format: Floating Point
• Clock Freq (max): 80MHz
• Mips: 80
• Device Input Clock Speed: 80MHz
• Ram Size: 512KB
• Operating Supply Voltage (typ): 2.5/3.3V
• Operating Supply Voltage (min): 2.37/3.13V
• Operating Supply Voltage (max): 2.63/3.47V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 400
• Package Type: BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

The load capacitance should include the processor’s
package capacitance (C
includes driving the load high and then back low. Address
and data pins can drive high and low at a maximum rate of
Table 29. ADSP-21160M Operation Types vs. Input Current
1
2
REV. 0
Peak Activity=I
these calculations.
These assume a 2:1 core clock ratio. For more information on ratios and clocks (t
Operation
Instruction Type
Instruction Fetch
Core Memory Access
Internal Memory DMA
External Memory DMA
Data bit pattern for core
memory access and DMA
DDINPEAK
, High Activity=I
2
IN
). The switching frequency
Peak Activity
Multifunction
Cache
2 per t
(DM 64 and PM 64)
1 per 2 t
1 per external port cycle ( 64)
Worst case
DDINHIGH
CK
, and Low Activity=I
CCLK
cycle
cycles
1
DDINLOW
–43–
. The state of the PEYEN bit (SIMD versus SISD mode) does not influence
1/(2t
frequency of 1/t
can switch on each cycle.
CK
High Activity
Multifunction
Internal Memory
1 per t
1 per 2 t
1 per external port cycle ( 64)
Random
(DM 64)
and t
CK
). The write strobe can switch every cycle at a
CCLK
CK
CCLK
cycle
), see the timing ratio definitions
cycles
CK
1
. Select pins switch at 1/(2t
ADSP-21160M
Low Activity
Single Function
Internal Memory
None
None
None
N/A
on page
CK
15.
), but selects
1