ADSP-21160MKBZ-80 Analog Devices Inc, ADSP-21160MKBZ-80 Datasheet - Page 20

• Manufacturer Part Number: ADSP-21160MKBZ-80
• Description: 32bit SHARC W/SIMD Capability
• Manufacturer: Analog Devices Inc
• Series: SHARC®r
• Type: Floating Pointr

Specifications of ADSP-21160MKBZ-80

• Interface: Host Interface, Link Port, Serial Port
• Clock Rate: 80MHz
• Non-volatile Memory: External
• On-chip Ram: 512kB
• Voltage - I/o: 3.30V
• Voltage - Core: 2.50V
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 400-BGA
• Device Core Size: 32b
• Architecture: Enhanced Harvard
• Format: Floating Point
• Clock Freq (max): 80MHz
• Mips: 80
• Device Input Clock Speed: 80MHz
• Ram Size: 512KB
• Operating Supply Voltage (typ): 2.5/3.3V
• Operating Supply Voltage (min): 2.37/3.13V
• Operating Supply Voltage (max): 2.63/3.47V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 400
• Package Type: BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

ADSP-21160M
Memory Write—Bus Master
Use these specifications for asynchronous interfacing to
memories (and memory-mapped peripherals) without
reference to CLKIN. These specifications apply when the
ADSP-21160M is the bus master accessing external
Table 10. Memory Write—Bus Master
1
2
3
4
ACK Delay/Setup: User must meet t
The falling edge of MSx, BMS is referenced.
Note that timing for ACK, DATA, RDx, WRx, and DMAG strobe timing parameters only applies to asynchronous access mode.
See
Parameter
Timing Requirements:
t
t
t
t
Switching Characteristics:
t
t
t
t
t
t
t
t
t
t
W = (number of wait states specified in WAIT register) × t
H = t
HI = t
I = t
DAAK
DSAK
SAKC
HAKC
DAWH
DAWL
WW
DDWH
DWHA
DWHD
DATRWH
WWR
DDWR
WDE
Example System Hold Time Calculation on page 44
CK
CK
CK
(if a bus idle cycle occurs, as specified in WAIT register; otherwise I = 0).
(if an address hold cycle occurs, as specified in WAIT register; otherwise H = 0).
(if an address hold cycle or bus idle cycle occurs, as specified in WAIT register; otherwise HI = 0).
ACK Delay from Address, Selects
ACK Delay from WRx Low
ACK Setup to CLKIN
ACK Hold After CLKIN
Address, CIF, Selects to WRx
Deasserted
Address, CIF, Selects to WRx Low
WRx Pulse width
Data Setup before WRx High
Address Hold after WRx Deasserted
Data Hold after WRx Deasserted
Data Disable after WRx Deasserted
WRx High to WRx, RDx, DMAGx
Low
Data Disable before WRx or RDx Low
WRx Low to Data Enabled
3
DAAK
2,3
or t
3
DSAK
or t
1,3
SAKC
1,3
for calculation of hold times given capacitive and dc loads.
for deassertion of ACK (Low), all three specifications must be met for assertion of ACK (High).
1,3
3
3
1,2
2
3,4
3
–20–
CK
Min
0.5t
1
t
0.25t
t
t
0.25t
0.25t
0.25t
0.5t
0.25t
–0.25t
CK
CK
CK
.
memory space in asynchronous access mode. Note that
timing for ACK, DATA, RDx, WRx, and DMAG strobe
timing parameters only applies to asynchronous access
mode.
– 0.25t
– 0.5t
– 0.25t
CCLK
CCLK
CCLK
CCLK
CCLK
CCLK
CCLK
CCLK
+3
– 1+HI
CCLK
– 3
– 1+H
– 1+H
– 2+H
– 1+I
CCLK
CCLK
– 1
– 1+W
– 12.5+W
– 3+W
Max
t
t
0.25t
CK
CK
– 0.75t
– 0.5t
CCLK
CCLK
+2+H
CCLK
–12+W
– 11+W
REV. 0
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns