ADSP-21160MKBZ-80 Analog Devices Inc, ADSP-21160MKBZ-80 Datasheet - Page 19

• Manufacturer Part Number: ADSP-21160MKBZ-80
• Description: 32bit SHARC W/SIMD Capability
• Manufacturer: Analog Devices Inc
• Series: SHARC®r
• Type: Floating Pointr

Specifications of ADSP-21160MKBZ-80

• Interface: Host Interface, Link Port, Serial Port
• Clock Rate: 80MHz
• Non-volatile Memory: External
• On-chip Ram: 512kB
• Voltage - I/o: 3.30V
• Voltage - Core: 2.50V
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 400-BGA
• Device Core Size: 32b
• Architecture: Enhanced Harvard
• Format: Floating Point
• Clock Freq (max): 80MHz
• Mips: 80
• Device Input Clock Speed: 80MHz
• Ram Size: 512KB
• Operating Supply Voltage (typ): 2.5/3.3V
• Operating Supply Voltage (min): 2.37/3.13V
• Operating Supply Voltage (max): 2.63/3.47V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 400
• Package Type: BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Memory Read—Bus Master
Use these specifications for asynchronous interfacing to
memories (and memory-mapped peripherals) without
reference to CLKIN. These specifications apply when the
ADSP-21160M is the bus master accessing external
Table 9. Memory Read—Bus Master
1
2
3
4
5
REV. 0
Data Delay/Setup: User must meet t
The falling edge of MSx, BMS is referenced.
Note that timing for ACK, DATA, RDx, WRx, and DMAG strobe timing parameters only applies to asynchronous access mode.
Data Hold: User must meet t
hold times given capacitive and dc loads.
ACK Delay/Setup: User must meet t
Parameter
Timing Requirements:
t
t
t
t
t
t
t
t
t
Switching Characteristics:
t
t
t
t
W = (number of wait states specified in WAIT register)
HI = t
H = t
DAD
DRLD
HDA
SDS
HDRH
DAAK
DSAK
SAKC
HAKC
DRHA
DARL
RW
RWR
CK
CK
(if an address hold cycle occurs as specified in WAIT register; otherwise H = 0).
(if an address hold cycle or bus idle cycle occurs, as specified in WAIT register; otherwise HI = 0).
Address, CIF, Selects Delay to Data
Valid
RDx Low to Data Valid
Data Hold from Address, Selects
Data Setup to RDx High
Data Hold from RDx High
ACK Delay from Address, Selects
ACK Delay from RDx Low
ACK Setup to CLKIN
ACK Hold After CLKIN
Address, CIF, Selects Hold After RDx
High
Address, CIF, Selects to RDx Low
RDx Pulse width
RDx High to WRx, RDx, DMAGx Low
1,2
3
HDA
or t
DAD
DAAK
HDRH
, t
, t
DRLD
in asynchronous access mode. See
DSAK
3
, or t
, or t
SDS.
3,5
SAKC
1,3
1
3
3,4
for deassertion of ACK (Low), all three specifications must be met for assertion of ACK (High).
Figure 15. Memory Read—Bus Master
3,5
4
2,5
2
3
–19–
t
CK
Example System Hold Time Calculation on page 44
.
memory space in asynchronous access mode. Note that
timing for ACK, DATA, RDx, WRx, and DMAG strobe
timing parameters only applies to asynchronous access
mode.
Min
0
8
1
0.5t
1
0.25t
0.25t
t
0.5t
CK
– 0.5t
CCLK
CCLK
CCLK
CCLK
+3
– 1+HI
CCLK
– 3
– 1+H
– 1+W
Max
t
0.75t
t
t
CK
CK
CK
– 0.75t
– 0.25t
– 0.5t
CK
– 11+W
CCLK
ADSP-21160M
CCLK
CCLK
– 12+W
– 11+W
– 11+W
for the calculation of
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns