ADSP-21160MKBZ-80 Analog Devices Inc, ADSP-21160MKBZ-80 Datasheet - Page 22

• Manufacturer Part Number: ADSP-21160MKBZ-80
• Description: 32bit SHARC W/SIMD Capability
• Manufacturer: Analog Devices Inc
• Series: SHARC®r
• Type: Floating Pointr

Specifications of ADSP-21160MKBZ-80

• Interface: Host Interface, Link Port, Serial Port
• Clock Rate: 80MHz
• Non-volatile Memory: External
• On-chip Ram: 512kB
• Voltage - I/o: 3.30V
• Voltage - Core: 2.50V
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 400-BGA
• Device Core Size: 32b
• Architecture: Enhanced Harvard
• Format: Floating Point
• Clock Freq (max): 80MHz
• Mips: 80
• Device Input Clock Speed: 80MHz
• Ram Size: 512KB
• Operating Supply Voltage (typ): 2.5/3.3V
• Operating Supply Voltage (min): 2.37/3.13V
• Operating Supply Voltage (max): 2.63/3.47V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 400
• Package Type: BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

ADSP-21160M
Synchronous Read/Write—Bus Master
Use these specifications for interfacing to external memory
systems that require CLKIN—relative timing or for
accessing a slave ADSP-21160M (in multiprocessor
memory space). These synchronous switching characteris-
tics are also valid during asynchronous memory reads and
writes except where noted (see
on page 19
Table 11. Synchronous Read/Write—Bus Master
1
2
3
Note that timing for ACK, DATA, RDx, WRx, and DMAG strobe timing parameters only applies to synchronous access mode.
Applies to broadcast write, master precharge of ACK.
Applies only when the DSP drives a bus operation; CLKOUT held inactive or three-state otherwise, For more information, see the System Design chapter
in the ADSP-2116x SHARC DSP Hardware Reference.
Parameter
Timing Requirements:
t
t
t
t
Switching Characteristics:
t
t
t
t
t
t
t
t
t
t
t
t
t
t
SSDATI
HSDATI
SACKC
HACKC
DADDO
HADDO
DPGO
DRDO
DWRO
DRWL
DDATO
HDATO
DACKMO
ACKMTR
DCKOO
CKOP
CKWH
CKWL
and
Memory Write—Bus Master on page
Data Setup Before CLKIN
Data Hold After CLKIN
ACK Setup Before CLKIN
ACK Hold After CLKIN
Address, MSx, BMS, BRST, CIF Delay After CLKIN
Address, MSx, BMS, BRST, CIF Hold After CLKIN
PAGE Delay After CLKIN
RDx High Delay After CLKIN
WRx High Delay After CLKIN
RDx/WRx Low Delay After CLKIN
Data Delay After CLKIN
Data Hold After CLKIN
ACK Delay After CLKIN
ACK Disable Before CLKIN
CLKOUT Delay After CLKIN
CLKOUT Period
CLKOUT Width High
CLKOUT Width Low
Memory Read—Bus Master
1
1
2
1
1
2
1
1
20).
–22–
When accessing a slave ADSP-21160M, these switching
characteristics must meet the slave’s timing requirements
for synchronous read/writes (see
Read/Write—Bus Slave on page
ADSP-21160M must also meet these (bus master) timing
requirements for data and acknowledge setup and hold
times.
Min
5.5
1
0.5t
1
1.5
1.5
0.25t
0.25t
0.25t
1.5
0.25t
0.25t
2
t
t
t
CK
CK
CK
/2 – 2
/2 – 2
– 1
CCLK
CCLK
CCLK
CCLK
CCLK
CCLK
+3
+3
– 1
– 1
– 1
– 3
24). The slave
Synchronous
Max
10
11
0.25t
0.25t
0.25t
12.5
0.25t
5
t
t
t
CK
CK
CK
3
/2+2
/2+2
+1
CCLK
CCLK
CCLK
CCLK
3
3
+9
+9
+9
+9
REV. 0
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns