ADSP-21160MKBZ-80 Analog Devices Inc, ADSP-21160MKBZ-80 Datasheet - Page 26

• Manufacturer Part Number: ADSP-21160MKBZ-80
• Description: 32bit SHARC W/SIMD Capability
• Manufacturer: Analog Devices Inc
• Series: SHARC®r
• Type: Floating Pointr

Specifications of ADSP-21160MKBZ-80

• Interface: Host Interface, Link Port, Serial Port
• Clock Rate: 80MHz
• Non-volatile Memory: External
• On-chip Ram: 512kB
• Voltage - I/o: 3.30V
• Voltage - Core: 2.50V
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 400-BGA
• Device Core Size: 32b
• Architecture: Enhanced Harvard
• Format: Floating Point
• Clock Freq (max): 80MHz
• Mips: 80
• Device Input Clock Speed: 80MHz
• Ram Size: 512KB
• Operating Supply Voltage (typ): 2.5/3.3V
• Operating Supply Voltage (min): 2.37/3.13V
• Operating Supply Voltage (max): 2.63/3.47V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 400
• Package Type: BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

ADSP-21160M
Multiprocessor Bus Request and Host Bus Request
Use these specifications for passing of bus mastership
between multiprocessing ADSP-21160Ms (BRx) or a host
processor (HBR, HBG).
Table 13. Multiprocessor Bus Request and Host Bus Request
1
2
Only required for recognition in the current cycle.
(O/D) = open drain, (A/D) = active drive.
Parameter
Timing Requirements:
t
t
t
t
t
t
t
t
t
t
t
Switching Characteristics:
t
t
t
t
t
t
t
t
t
t
t
HBGRCSV
SHBRI
HHBRI
SHBGI
HHBGI
SBRI
HBRI
SPAI
HPAI
SRPBAI
HRPBAI
DHBGO
HHBGO
DBRO
HBRO
DPASO
TRPAS
DPAMO
PATR
DRDYCS
TRDYHG
ARDYTR
HBG Low to RDx/WRx/CS Valid
HBR Setup Before CLKIN
HBR Hold After CLKIN
HBG Setup Before CLK/=’]IN
HBG Hold After CLKIN High
BRx, PA Setup Before CLKIN
BRx, PA Hold After CLKIN High
PA Setup Before CLKIN
PA Hold After CLKIN High
RPBA Setup Before CLKIN
RPBA Hold After CLKIN
HBG Delay After CLKIN
HBG Hold After CLKIN
BRx Delay After CLKIN
BRx Hold After CLKIN
PA Delay After CLKIN, Slave
PA Disable After CLKIN, Slave
PA Delay After CLKIN, Master
PA Disable Before CLKIN, Master
REDY (O/D) or (A/D) Low from CS and HBR Low
REDY (O/D) Disable or REDY (A/D) High from HBG
REDY (A/D) Disable from CS or HBR High
1
1
–26–
2
2
2
Min
6
1
6
1
9
1
9
1
6
2
2
1.5
1.5
0.25t
t
CK
+25
CCLK
– 5
Max
19
7
8
8
0.25t
0.5t
11
CK
CCLK
+9
REV. 0
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns