ADSP-21160MKBZ-80 Analog Devices Inc, ADSP-21160MKBZ-80 Datasheet - Page 2

• Manufacturer Part Number: ADSP-21160MKBZ-80
• Description: 32bit SHARC W/SIMD Capability
• Manufacturer: Analog Devices Inc
• Series: SHARC®r
• Type: Floating Pointr

Specifications of ADSP-21160MKBZ-80

• Interface: Host Interface, Link Port, Serial Port
• Clock Rate: 80MHz
• Non-volatile Memory: External
• On-chip Ram: 512kB
• Voltage - I/o: 3.30V
• Voltage - Core: 2.50V
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 400-BGA
• Device Core Size: 32b
• Architecture: Enhanced Harvard
• Format: Floating Point
• Clock Freq (max): 80MHz
• Mips: 80
• Device Input Clock Speed: 80MHz
• Ram Size: 512KB
• Operating Supply Voltage (typ): 2.5/3.3V
• Operating Supply Voltage (min): 2.37/3.13V
• Operating Supply Voltage (max): 2.63/3.47V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 400
• Package Type: BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

ADSP-21160M
FEATURES (CONTINUED)
Single Instruction Multiple Data (SIMD)
Parallelism in Buses and Computational Units Allows:
4M Bit On-Chip Dual-Ported SRAM for Independent
DMA Controller supports:
4G Word Address Range for Off-Chip Memory
Memory Interface Supports Programmable Wait State
Multiprocessing Support Provides:
Serial Ports Provide:
Architecture Provides:
Two Computational Processing Elements
Concurrent Execution—Each Processing Element
Code Compatibility—at Assembly Level, Uses the
Single-cycle Execution (with or without SIMD) of: A
Transfers Between Memory and Core at up to Four
Accelerated FFT Butterfly Computation Through a
Access by Core Processor, Host, and DMA
14 Zero-Overhead DMA Channels for Transfers Between
64-Bit Background DMA Transfers at Core Clock Speed,
560M Bytes/s Transfer Rate Over IOP Bus
Host Processor Interface to 16- and 32-Bit
Generation and Page-Mode for Off-Chip Memory
Glueless Connection for Scalable DSP Multiprocessing
Distributed On-Chip Bus Arbitration for Parallel Bus
Six Link Ports for Point-To-Point Connectivity and Array
Two 40M Bit/s Synchronous Serial Ports with
Independent Transmit and Receive Functions
TDM Support for T1 and E1 Interfaces
64-Bit Wide Synchronous External Port Provides:
Glueless Connection to Asynchronous and SBSRAM
Up to 40 MHz Operation
Executes the Same Instruction, but Operates on
Different Data
Same Instruction Set as the ADSP-2106x
SHARC DSPs
Multiply Operation, An ALU Operation, A Dual
Memory Read or Write, and An Instruction Fetch
32-Bit Floating- or Fixed-Point Words per Cycle
Multiply with Add and Subtract
ADSP-21160M Internal Memory and External
Memory, External Peripherals, Host Processor, Serial
Ports, or Link Ports
in Parallel with Full-Speed Processor Execution
Microprocessors
Architecture
Connect of up to Six ADSP-21160Ms plus Host
Multiprocessing
Companding Hardware
External Memories
–2–
GENERAL DESCRIPTION
The ADSP-21160M SHARC DSP is the first processor in
a new family featuring Analog Devices’ Super Harvard
Architecture. Easing portability, the ADSP-21160M is
application source code compatible with first generation
ADSP-2106x SHARC DSPs in SISD (Single Instruction,
Single Data) mode. To take advantage of the processor’s
SIMD (Single Instruction, Multiple Data) capability, some
code changes are needed. Like other SHARCs, the
ADSP-21160M is a 32-bit processor that is optimized for
high performance DSP applications. The ADSP-21160M
includes an 80 MHz core, a dual-ported on-chip SRAM, an
integrated I/O processor with multiprocessing support, and
multiple internal buses to eliminate I/O bottlenecks.
The ADSP-21160M introduces Single-Instruction,
Multiple-Data (SIMD) processing. Using two computa-
tional units (ADSP-2106x SHARC DSPs have one), the
ADSP-21160M can double performance versus the
ADSP-2106x on a range of DSP algorithms.
Fabricated in a state of the art, high speed, low power
CMOS process, the ADSP-21160M has a 12.5 ns instruc-
tion cycle time. With its SIMD computational hardware
running at 80 MHz, the ADSP-21160M can perform 480
million math operations per second.
Table 1
ADSP-21160M.
Table 1. ADSP-21160M Benchmarks
These benchmarks provide single-channel extrapolations of
measured dual-channel processing performance. For more
information on benchmarking and optimizing DSP code for
single- and dual-channel processing, see Analog Devices’s
website.
The ADSP-21160M continues SHARC’s industry-leading
standards of integration for DSPs, combining a
high-performance 32-bit DSP core with integrated, on-chip
system features. These features include a 4M bit dual
ported SRAM memory, host processor interface, I/O
processor that supports 14 DMA channels, two serial ports,
six link ports, external parallel bus, and glueless
multiprocessing.
Benchmark Algorithm
1024 Point Complex FFT (Radix 4, with
reversal)
FIR Filter (per tap)
IIR Filter (per biquad)
Matrix Multiply (pipelined)
[3 3]
Matrix Multiply (pipelined)
[4 4]
Divide (y/x)
Inverse Square Root
DMA Transfer Rate
shows performance benchmarks for the
[3 1]
[4 1]
Speed
115 µs
6.25 ns
25 ns
56.25 ns
100 ns
37.5 ns
56.25 ns
560M Bytes/s
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