LPC2364HBD100/LQFP100/TRAYBDP/

LPC2364HBD100

Manufacturer Part NumberLPC2364HBD100
DescriptionLPC2364HBD100/LQFP100/TRAYBDP/
ManufacturerNXP Semiconductors
SeriesLPC2300
LPC2364HBD100 datasheet
 

Specifications of LPC2364HBD100

Core ProcessorARM7Core Size16/32-Bit
Speed72MHzConnectivityCAN, Ethernet, I²C, Microwire, SPI, SSI, SSP, UART/USART, USB
PeripheralsBrown-out Detect/Reset, DMA, I²S, POR, PWM, WDTNumber Of I /o70
Program Memory Size128KB (128K x 8)Program Memory TypeFLASH
Ram Size34K x 8Voltage - Supply (vcc/vdd)3 V ~ 3.6 V
Data ConvertersA/D 6x10b; D/A 1x10bOscillator TypeInternal
Operating Temperature-40°C ~ 125°CPackage / Case100-LQFP
Processor SeriesLPC23CoreARM7TDMI-S
3rd Party Development ToolsMDK-ARM, RL-ARM, ULINK2, SAB-TFBGA100Lead Free Status / RoHS StatusLead free / RoHS Compliant
Eeprom Size-  
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LPC2364/65/66/67/68
Single-chip 16-bit/32-bit microcontrollers; up to 512 kB flash
with ISP/IAP, Ethernet, USB 2.0, CAN, and 10-bit ADC/DAC
Rev. 06 — 1 February 2010
1. General description
The LPC2364/65/66/67/68 microcontrollers are based on a 16-bit/32-bit ARM7TDMI-S
CPU with real-time emulation that combines the microcontroller with up to 512 kB of
embedded high-speed flash memory. A 128-bit wide memory interface and a unique
accelerator architecture enable 32-bit code execution at the maximum clock rate. For
critical performance in interrupt service routines and DSP algorithms, this increases
performance up to 30 % over Thumb mode. For critical code size applications, the
alternative 16-bit Thumb mode reduces code by more than 30 % with minimal
performance penalty.
The LPC2364/65/66/67/68 are ideal for multi-purpose serial communication applications.
They incorporate a 10/100 Ethernet Media Access Controller (MAC), USB full speed
device with 4 kB of endpoint RAM (LPC2364/66/68 only), four UARTs, two CAN channels
(LPC2364/66/68 only), an SPI interface, two Synchronous Serial Ports (SSP), three I
interfaces, and an I
with an on-chip 4 MHz internal oscillator, SRAM of up to 32 kB, 16 kB SRAM for Ethernet,
8 kB SRAM for USB and general purpose use, together with 2 kB battery powered SRAM
make these devices very well suited for communication gateways and protocol
converters. Various 32-bit timers, an improved 10-bit ADC, 10-bit DAC, one PWM unit, a
CAN control unit (LPC2364/66/68 only), and up to 70 fast GPIO lines with up to 12 edge
or level sensitive external interrupt pins make these microcontrollers particularly suitable
for industrial control and medical systems.
2. Features
ARM7TDMI-S processor, running at up to 72 MHz
Up to 512 kB on-chip flash program memory with In-System Programming (ISP) and
In-Application Programming (IAP) capabilities. Flash program memory is on the ARM
local bus for high performance CPU access.
8 kB/32 kB of SRAM on the ARM local bus for high performance CPU access.
16 kB SRAM for Ethernet interface. Can also be used as general purpose SRAM.
8 kB SRAM for general purpose DMA use also accessible by the USB.
Dual Advanced High-performance Bus (AHB) system that provides for simultaneous
Ethernet DMA, USB DMA, and program execution from on-chip flash with no
contention between those functions. A bus bridge allows the Ethernet DMA to access
the other AHB subsystem.
Advanced Vectored Interrupt Controller (VIC), supporting up to 32 vectored interrupts.
General Purpose DMA controller (GPDMA) on AHB that can be used with the SSP
serial interfaces, the I
port, as well as for memory-to-memory transfers.
2
S interface. This blend of serial communications interfaces combined
2
S port, and the Secure Digital/MultiMediaCard (SD/MMC) card
Product data sheet
2
C

LPC2364HBD100 Summary of contents

  • Page 1

    LPC2364/65/66/67/68 Single-chip 16-bit/32-bit microcontrollers 512 kB flash with ISP/IAP, Ethernet, USB 2.0, CAN, and 10-bit ADC/DAC Rev. 06 — 1 February 2010 1. General description The LPC2364/65/66/67/68 microcontrollers are based on a 16-bit/32-bit ARM7TDMI-S CPU with real-time emulation ...

  • Page 2

    ... NXP Semiconductors Serial interfaces: Ethernet MAC with associated DMA controller. These functions reside on an independent AHB. USB 2.0 full-speed device with on-chip PHY and associated DMA controller (LPC2364/66/68 only). Four UARTs with fractional baud rate generation, one with modem control I/O, one with IrDA support, all with FIFO ...

  • Page 3

    ... Versatile pin function selections allow more possibilities for using on-chip peripheral functions. 3. Applications Industrial control Medical systems Protocol converter Communications 4. Ordering information Table 1. Ordering information Type number Package Name LPC2364FBD100 LQFP100 LPC2364HBD100 LQFP100 LPC2364FET100 TFBGA100 LPC2365FBD100 LQFP100 LPC2366FBD100 LQFP100 LPC2367FBD100 LQFP100 LPC2368FBD100 LQFP100 LPC2368FET100 TFBGA100 LPC2364_65_66_67_68_6 ...

  • Page 4

    ... Ordering options Table 2. Ordering options Type number Flash SRAM (kB) (kB) Local Ethernet GP/USB RTC bus buffers LPC2364FBD100 128 LPC2364HBD100 128 LPC2364FET100 128 LPC2365FBD100 256 LPC2366FBD100 256 LPC2367FBD100 512 LPC2368FBD100 512 LPC2368FET100 512 Ethernet USB SD/MMC GP DMA device + Total 4 kB FIFO ...

  • Page 5

    ... NXP Semiconductors 5. Block diagram LPC2364/65/66/67/68 P0, P1, P2, P3, P4 HIGH-SPEED GPI/O 70 PINS TOTAL ETHERNET RMII(8) MAC WITH DMA EINT3 to EINT0 EXTERNAL INTERRUPTS P0 × CAP0/CAP1/ CAPTURE/COMPARE CAP2/CAP3 TIMER0/TIMER1/ 4 × MAT2, TIMER2/TIMER3 2 × MAT0/MAT1/ MAT3 6 × PWM1 2 × PCAP1 LEGACY GPI/O P0 PINS TOTAL 6 × AD0 ...

  • Page 6

    ... NXP Semiconductors 6. Pinning information 6.1 Pinning Fig 2. Fig 3. Table 3. Pin allocation table Pin Symbol Pin Symbol Row A 1 TDO 2 5 P1[10]/ENET_RXD1 6 9 P0[7]/I2STX_CLK/ 10 SCK1/MAT2[1] Row B 1 TMS 2 LPC2364_65_66_67_68_6 Product data sheet 1 LPC2364FBD100 LPC2365FBD100 LPC2366FBD100 LPC2367FBD100 LPC2368FBD100 25 LPC2364/65/66/67/68 pinning ball A1 ...

  • Page 7

    ... NXP Semiconductors Table 3. Pin allocation table Pin Symbol Pin Symbol 5 P1[9]/ENET_RXD0 6 9 P2[0]/PWM1[1]/ 10 TXD1/TRACECLK Row C 1 TCK 2 5 P1[8]/ENET_CRS Row D 1 P0[24]/AD0[1]/ 2 I2SRX_WS/CAP3[1] 5 P1[0]/ENET_TXD0 6 9 P2[4]/PWM1[5]/ 10 DSR1/TRACESYNC Row SSA 5 P0[23]/AD0[0]/ 6 I2SRX_CLK/CAP3[0] 9 P2[7]/RD2/ 10 RTS1/TRACEPKT2 ...

  • Page 8

    ... NXP Semiconductors Table 3. Pin allocation table Pin Symbol Pin Symbol Row J 1 P0[28]/SCL0 2 5 P1[22]/MAT1[ P2[13]/EINT3/ 10 MCIDAT3/I2STX_SDA Row K 1 P3[26]/MAT0[1]/ 2 PWM1[3] 5 P1[23]/PWM1[4]/ 6 MISO0 9 P0[11]/RXD2/ 10 SCL2/MAT3[1] 6.2 Pin description Table 4. Pin description Symbol Pin Ball P0[0] to P0[31] ...

  • Page 9

    ... NXP Semiconductors Table 4. Pin description …continued Symbol Pin Ball [1] [1] P0[6 I2SRX_SDA/ SSEL1/MAT2[0] [1] [1] P0[7 I2STX_CLK/ SCK1/MAT2[1] [1] P0[8 I2STX_WS/ MISO1/MAT2[2] [1] P0[9]/ 76 A10 I2STX_SDA/ MOSI1/MAT2[3] [1] P0[10]/TXD2 SDA2/MAT3[0] [1] [1] P0[11]/RXD2 SCL2/MAT3[1] [1] P0[15]/TXD1/ 62 F10 SCK0/SCK [1] [1] P0[16]/RXD1 SSEL0/SSEL [1] [1] P0[17]/CTS1/ ...

  • Page 10

    ... NXP Semiconductors Table 4. Pin description …continued Symbol Pin Ball [1] [1] P0[18]/DCD1 MOSI0/MOSI [1] P0[19]/DSR1/ 59 G10 MCICLK/SDA1 [1] P0[20]/DTR1 MCICMD/SCL1 [1] P0[21]/RI1 MCIPWR/RD1 [1] P0[22]/RTS1/ 56 H10 MCIDAT0/TD1 [2] [2] P0[23]/AD0[0 I2SRX_CLK/ CAP3[0] [2] P0[24]/AD0[1 I2SRX_WS/ CAP3[1] [2] P0[25]/AD0[2 I2SRX_SDA/ TXD3 [3] P0[26]/AD0[3]/ ...

  • Page 11

    ... NXP Semiconductors Table 4. Pin description …continued Symbol Pin Ball [4] [4] P0[27]/SDA0 25 J2 [4] [4] P0[28]/SCL0 24 J1 [5] [5] P0[29]/USB_D [5] P0[30]/USB_D− P1[0] to P1[31] [1] P1[0 ENET_TXD0 [1] [1] P1[1 ENET_TXD1 [1] [1] P1[4 ENET_TX_EN [1] P1[8 ENET_CRS [1] [1] P1[9 ENET_RXD0 [1] [1] P1[10 ENET_RXD1 ...

  • Page 12

    ... NXP Semiconductors Table 4. Pin description …continued Symbol Pin Ball [1] [1] P1[20]/PWM1[2 SCK0 [1] [1] P1[21]/PWM1[3 SSEL0 [1] [1] P1[22]/MAT1[ [1] [1] P1[23]/PWM1[4 MISO0 [1] P1[24]/PWM1[5 MOSI0 [1] P1[25]/MAT1[ [1] [1] P1[26]/PWM1[6 CAP0[0] [1] [1] P1[27]/CAP0[ [1] [1] P1[28 PCAP1[0]/ MAT0[0] [1] P1[29]/ ...

  • Page 13

    ... NXP Semiconductors Table 4. Pin description …continued Symbol Pin Ball [1] P2[1]/PWM1[2]/ 74 B10 RXD1/ PIPESTAT0 [1] P2[2]/PWM1[3 CTS1/ PIPESTAT1 [1] [1] P2[3]/PWM1[4 DCD1/ PIPESTAT2 [1] P2[4]/PWM1[5 DSR1/ TRACESYNC [1] P2[5]/PWM1[6]/ 68 D10 DTR1/ TRACEPKT0 [1] [1] P2[6]/PCAP1[0 RI1/ TRACEPKT1 [1] [1] P2[7]/RD2 RTS1/ ...

  • Page 14

    ... NXP Semiconductors Table 4. Pin description …continued Symbol Pin Ball [6] P2[11]/EINT1 MCIDAT1/ I2STX_CLK [6] P2[12]/EINT2/ 51 K10 MCIDAT2/ I2STX_WS [6] [6] P2[13]/EINT3 MCIDAT3/ I2STX_SDA P3[0] to P3[31] [1] P3[25]/MAT0[0 PWM1[2] [1] [1] P3[26]/MAT0[1 PWM1[3] P4[0] to P4[31] [1] P4[28]/MAT2[0 TXD3 [1] [1] P4[29]/MAT2[1 RXD3 ...

  • Page 15

    ... NXP Semiconductors Table 4. Pin description …continued Symbol Pin Ball [1] TCK 5 C1 [1] [1] RTCK 100 B2 RSTOUT 14 - [7] [7] RESET 17 F3 [8][9] XTAL1 22 H2 [8][9] XTAL2 23 G3 [8] [8] RTCX1 16 F2 [8] RTCX2 15, 31, B3, B7, SS 41, 55, C9, F1, 72, 97, G7, J6, [10 [11] [11 SSA V 28, 54, A3, C10, DD(3V3) ...

  • Page 16

    ... NXP Semiconductors [8] Pad provides special analog functionality. [9] When the main oscillator is not used, connect XTAL1 and XTAL2 as follows: XTAL1 can be left floating or can be grounded (grounding is preferred to reduce susceptibility to noise). XTAL2 should be left floating. [10] Pad provides special analog functionality. [11] Pad provides special analog functionality. ...

  • Page 17

    ... NXP Semiconductors The ARM7TDMI-S processor also employs a unique architectural strategy known as Thumb, which makes it ideally suited to high-volume applications with memory restrictions, or applications where code density is an issue. The key idea behind Thumb is that of a super-reduced instruction set. Essentially, the ARM7TDMI-S processor has two instruction sets: • ...

  • Page 18

    ... NXP Semiconductors 3.75 GB Fig 4. 7.5 Interrupt controller The ARM processor core has two interrupt inputs called Interrupt Request (IRQ) and Fast Interrupt Request (FIQ). The VIC takes 32 interrupt request inputs which can be programmed as FIQ or vectored IRQ types. The programmable assignment scheme means that priorities of interrupts from the various peripherals can be dynamically assigned and adjusted ...

  • Page 19

    ... NXP Semiconductors FIQs have the highest priority. If more than one request is assigned to FIQ, the VIC ORs the requests to produce the FIQ signal to the ARM processor. The fastest possible FIQ latency is achieved when only one request is classified as FIQ, because then the FIQ service routine can simply start dealing with that device ...

  • Page 20

    ... NXP Semiconductors • Single DMA and burst DMA request signals. Each peripheral connected to the GPDMA can assert either a burst DMA request or a single DMA request. The DMA burst size is set by programming the GPDMA. • Memory-to-memory, memory-to-peripheral, peripheral-to-memory, and peripheral-to-peripheral transfers. • ...

  • Page 21

    ... NXP Semiconductors Additionally, any pin on Port 0 and Port 2 (total of 42 pins) providing a digital function can be programmed to generate an interrupt on a rising edge, a falling edge, or both. The edge detection is asynchronous may operate when clocks are not present such as during Power-down mode. Each enabled interrupt can be used to wake up the chip from Power-down mode ...

  • Page 22

    ... NXP Semiconductors – Receive filtering. – Multicast and broadcast frame support for both transmit and receive. – Optional automatic Frame Check Sequence (FCS) insertion with Circular Redundancy Check (CRC) for transmit. – Selectable automatic transmit frame padding. – Over-length frame support for both transmit and receive allows any length frames. ...

  • Page 23

    ... NXP Semiconductors • Double buffer implementation for Bulk and Isochronous endpoints. 7.11 CAN controller and acceptance filters (LPC2364/66/68 only) The Controller Area Network (CAN serial communications protocol which efficiently supports distributed real-time control with a very high level of security. Its domain of application ranges from high-speed networks to low cost multiplex wiring. ...

  • Page 24

    ... NXP Semiconductors 7.13 10-bit DAC The DAC allows the LPC2364/65/66/67/68 to generate a variable analog output. The maximum output value of the DAC is V 7.13.1 Features • 10-bit DAC • Resistor string architecture • Buffered output • Power-down mode • Selectable output drive 7.14 UARTs The LPC2364/65/66/67/68 each contain four UARTs ...

  • Page 25

    ... NXP Semiconductors 7.16 SSP serial I/O controller The LPC2364/65/66/67/68 each contain two SSP controllers. The SSP controller is capable of operation on a SPI, 4-wire SSI, or Microwire bus. It can interact with multiple masters and slaves on the bus. Only a single master and a single slave can communicate on the bus during a given data transfer ...

  • Page 26

    ... NXP Semiconductors 7.18.1 Features • standard I • and I devices connected to the same bus lines. • Easy to configure as master, slave, or master/slave. • Programmable clocks allow versatile rate control. • Bidirectional data transfer between masters and slaves. • Multi-master bus (no central master). • ...

  • Page 27

    ... NXP Semiconductors 7.20 General purpose 32-bit timers/external event counters The LPC2364/65/66/67/68 include four 32-bit Timer/Counters. The Timer/Counter is designed to count cycles of the system derived clock or an externally-supplied clock. It can optionally generate interrupts or perform other actions at specified timer values, based on four match registers. The Timer/Counter also includes two capture inputs to trap the timer value when an input signal transitions, optionally generating an interrupt ...

  • Page 28

    ... NXP Semiconductors Three match registers can be used to provide a PWM output with both edges controlled. Again, the PWMMR0 match register controls the PWM cycle rate. The other match registers control the two PWM edge positions. Additional double edge controlled PWM outputs require only two match registers each, since the repetition rate is the same for all PWM outputs ...

  • Page 29

    ... NXP Semiconductors • Incorrect/Incomplete feed sequence causes reset/interrupt if enabled. • Flag to indicate watchdog reset. • Programmable 32-bit timer with internal prescaler. • Selectable time period from (T multiples of T • The Watchdog Clock (WDCLK) source can be selected from the RTC clock, the Internal RC oscillator (IRC), or the APB peripheral clock ...

  • Page 30

    ... NXP Semiconductors 7.24.1.1 Internal RC oscillator The IRC may be used as the clock source for the WDT, and/or as the clock that drives the PLL and subsequently the CPU. The nominal IRC frequency is 4 MHz. The IRC is trimmed to ±1 % accuracy. Upon power-up or any chip reset, the LPC2364/65/66/67/68 uses the IRC as the clock source ...

  • Page 31

    ... NXP Semiconductors When the main oscillator is initially activated, the wake-up timer allows software to ensure that the main oscillator is fully functional before the processor uses clock source and starts to execute instructions. This is important at power on, all types of Reset, and whenever any of the aforementioned functions are turned off for any reason. Since the ...

  • Page 32

    ... NXP Semiconductors On the wake-up of Sleep mode, if the IRC was used before entering Sleep mode, the code execution and peripherals activities will resume after 4 cycles expire. If the main external oscillator was used, the code execution will resume when 4096 cycles expire. The customers need to reconfigure the PLL and clock dividers accordingly. ...

  • Page 33

    ... NXP Semiconductors The first option assumes that power consumption is not a concern and the design ties the V DD(3V3) supply for both pads, the CPU, and peripherals. While this solution is simple, it does not support powering down the I/O pad ring “on the fly” while keeping the CPU and peripherals alive. The second option uses two power supplies ...

  • Page 34

    ... NXP Semiconductors 7.25.3 Code security (Code Read Protection - CRP) This feature of the LPC2364/65/66/67/68 allows user to enable different levels of security in the system so that access to the on-chip flash and use of the JTAG and ISP can be restricted. When needed, CRP is invoked by programming a specific pattern into a dedicated flash location ...

  • Page 35

    ... NXP Semiconductors 7.25.6 Memory mapping control The memory mapping control alters the mapping of the interrupt vectors that appear at the beginning at address 0x0000 0000. Vectors may be mapped to the bottom of the Boot ROM or the SRAM. This allows code running in different memory spaces to have control of the interrupts ...

  • Page 36

    ... NXP Semiconductors Since trace information is compressed the software debugger requires a static image of the code being executed. Self-modifying code can not be traced because of this restriction. 7.26.3 RealMonitor RealMonitor is a configurable software module, developed by ARM Inc., which enables real-time debug lightweight debug monitor that runs in the background while users debug their foreground application ...

  • Page 37

    ... NXP Semiconductors 8. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter V supply voltage (3.3 V) DD(3V3) V DC-to-DC converter supply voltage DD(DCDC)(3V3) (3 analog 3.3 V pad supply voltage DDA V input voltage on pin VBAT i(VBAT) V input voltage on pin VREF ...

  • Page 38

    ... NXP Semiconductors 9. Static characteristics Table 6. Static characteristics − ° ° +85 C for standard devices, amb Symbol Parameter V supply voltage (3.3 V) DD(3V3) V DC-to-DC converter DD(DCDC)(3V3) supply voltage (3 analog 3.3 V pad supply DDA voltage V input voltage on pin i(VBAT) VBAT V input voltage on pin ...

  • Page 39

    ... NXP Semiconductors Table 6. Static characteristics − ° ° +85 C for standard devices, amb Symbol Parameter I I/O latch-up current latch V input voltage I V output voltage O V HIGH-level input IH voltage V LOW-level input voltage IL V hysteresis voltage hys V HIGH-level output OH voltage V LOW-level output OL voltage ...

  • Page 40

    ... NXP Semiconductors Table 6. Static characteristics − ° ° +85 C for standard devices, amb Symbol Parameter USB pins (LPC2364/66/68 only) I OFF-state output OZ current V bus supply voltage BUS V differential input DI sensitivity voltage V differential common CM mode voltage range V single-ended receiver th(rs)se switching threshold voltage ...

  • Page 41

    ... NXP Semiconductors 9.1 Power-down mode I DD(IO) (μA) Fig 5. I (μA) Fig 6. LPC2364_65_66_67_68_6 Product data sheet −2 −4 −40 − 3 i(VBAT) DD(DCDC)(3V3) amb I/O maximum supply current I 40 BAT 3.3 V i(VBAT 3.0 V i(VBAT −40 − 3 DD(3V3) DD(DCDC)(3V3) RTC battery maximum supply current I mode Rev. 06 — ...

  • Page 42

    ... NXP Semiconductors I DD(DCDC)pd(3v3) Fig 7. 9.2 Deep power-down mode I DD(IO) (μA) Fig 8. LPC2364_65_66_67_68_6 Product data sheet 800 (μA) 600 400 V = 3.3 V DD(DCDC)(3V3) 200 V = 3.0 V DD(DCDC)(3V3) 0 −40 − ° 3 DD(3V3) i(VBAT) amb Total DC-to-DC converter supply current I in Power-down mode 300 ...

  • Page 43

    ... NXP Semiconductors I (μA) Fig 9. I DD(DCDC)dpd(3v3) Fig 10. Total DC-to-DC converter maximum supply current I LPC2364_65_66_67_68_6 Product data sheet 40 BAT 3.3 V i(VBAT 3.0 V i(VBAT −40 − 3 DD(3V3) DD(DCDC)(3V3) RTC battery maximum supply current I power-down mode 100 (μ 3.3 V DD(DCDC)(3V3 3.0 V DD(DCDC)(3V3) ...

  • Page 44

    ... NXP Semiconductors 10. Dynamic characteristics Table 7. Dynamic characteristics − ° ° +85 C for standard devices, amb [1] over specified ranges. Symbol Parameter ARM processor clock frequency f operating frequency oper External clock f oscillator frequency osc T clock cycle time cy(clk) t clock HIGH time CHCX t clock LOW time ...

  • Page 45

    ... NXP Semiconductors Table 8. Dynamic characteristics of USB pins (full-speed) Ω pF 1 Symbol Parameter t receiver jitter for paired transitions JR2 t EOP width at receiver EOPR1 t EOP width at receiver EOPR2 [1] Characterized but not implemented as production test. Guaranteed by design. Table 9. Dynamic characteristics of flash − ° ° ...

  • Page 46

    ... NXP Semiconductors 10.1 Timing Fig 11. External clock timing (with an amplitude of at least V T PERIOD differential data lines Fig 12. Differential data-to-EOP transition skew and EOP width shifting edges SCK MOSI MISO Fig 13. MISO line set-up time in SSP Master mode LPC2364_65_66_67_68_6 Product data sheet ...

  • Page 47

    ... NXP Semiconductors 11. ADC electrical characteristics Table 10. ADC characteristics − 2 3 DDA amb Symbol Parameter V analog input voltage IA C analog input capacitance ia E differential linearity error D E integral non-linearity L(adj) E offset error O E gain error G E absolute error T R voltage source interface ...

  • Page 48

    ... NXP Semiconductors 1023 1022 1021 1020 1019 1018 7 code out offset error E O (1) Example of an actual transfer curve. (2) The ideal transfer curve. (3) Differential linearity error (E (4) Integral non-linearity (E L(adj) (5) Center of a step of the actual transfer curve. Fig 14. ADC characteristics LPC2364_65_66_67_68_6 Product data sheet ...

  • Page 49

    ... NXP Semiconductors AD0[y] Fig 15. Suggested ADC interface - LPC2364/65/66/67/68 AD0[y] pin LPC2364_65_66_67_68_6 Product data sheet LPC23XX 20 kΩ SAMPLE Rev. 06 — 1 February 2010 LPC2364/65/66/67/68 Single-chip 16-bit/32-bit microcontrollers R vsi AD0[y] V EXT 002aac610 © NXP B.V. 2010. All rights reserved ...

  • Page 50

    ... NXP Semiconductors 12. DAC electrical characteristics Table 11. DAC electrical characteristics − 2 3 DDA amb Symbol Parameter E differential linearity error D E integral non-linearity L(adj) E offset error O E gain error G C load capacitance L R load resistance L 13. Application information 13.1 Suggested USB interface solutions (LPC2364/66/68 only) LPC23XX Fig 16 ...

  • Page 51

    ... NXP Semiconductors LPC23XX Fig 17. LPC2364/66/68 USB interface on a bus-powered device 13.2 XTAL1 input The input voltage to the on-chip oscillators is limited to 1 the oscillator is driven by a clock in slave mode recommended that the input be coupled through a capacitor with C = 100 pF. To limit the input voltage to the specified range, choose an additional ...

  • Page 52

    ... NXP Semiconductors 14. Package outline LQFP100: plastic low profile quad flat package; 100 leads; body 1 pin 1 index 100 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 1.45 mm 1.6 0.25 0.05 1.35 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. ...

  • Page 53

    ... NXP Semiconductors TFBGA100: plastic thin fine-pitch ball grid array package; 100 balls; body 0.7 mm ball A1 index area ball index area DIMENSIONS (mm are the original dimensions) A UNIT max 0.4 0.8 0.5 mm 1.2 0.3 0.65 0.4 OUTLINE VERSION IEC SOT926 Fig 20. Package outline SOT926-1 (TFBGA100) ...

  • Page 54

    ... NXP Semiconductors 15. Abbreviations Table 12. Acronym ADC AHB AMBA APB BOD CAN DAC DCC DMA DSP EOP ETM GPIO IrDA JTAG MII MIIM PHY PLL PWM RMII SE0 SPI SSI SSP TTL UART USB LPC2364_65_66_67_68_6 Product data sheet Abbreviations Description Analog-to-Digital Converter ...

  • Page 55

    ... Section 13.3 “XTAL and RTC Printed-Circuit Board (PCB) layout • Added table note for XTAL1 and XTAL2 pins in 20090409 Product data sheet • Added part LPC2364HBD100. • Section 7.2: Added sentence clarifying SRAM speeds for LPC2364HBD. • Table 5: Updated V min/max. esd • ...

  • Page 56

    ... Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...

  • Page 57

    ... NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ ...

  • Page 58

    ... NXP Semiconductors 19. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 3 4.1 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 4 5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 5 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 6 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 8 7 Functional description . . . . . . . . . . . . . . . . . . 16 7.1 Architectural overview . . . . . . . . . . . . . . . . . . 16 7.2 On-chip flash programming memory . . . . . . . 17 7.3 On-chip SRAM . . . . . . . . . . . . . . . . . . . . . . . . 17 7.4 Memory map ...

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    ... NXP Semiconductors 13.3 XTAL and RTC Printed-Circuit Board (PCB) layout guidelines . . . . . . . . . . . . . . . . . 51 14 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 52 15 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 54 16 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 55 17 Legal information 17.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 56 17.2 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 17.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 17.4 Trademarks Contact information Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 LPC2364/65/66/67/68 Single-chip 16-bit/32-bit microcontrollers Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘ ...