LPC2364HBD100 NXP Semiconductors, LPC2364HBD100 Datasheet - Page 24

• Manufacturer Part Number: LPC2364HBD100
• Description: LPC2364HBD100/LQFP100/TRAYBDP/
• Manufacturer: NXP Semiconductors
• Series: LPC2300r

Specifications of LPC2364HBD100

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 72MHz
• Connectivity: CAN, Ethernet, I²C, Microwire, SPI, SSI, SSP, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 34K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 6x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 100-LQFP
• Processor Series: LPC23
• Core: ARM7TDMI-S
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, SAB-TFBGA100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

NXP Semiconductors
LPC2364_65_66_67_68_6
Product data sheet
7.13.1 Features
7.14.1 Features
7.15.1 Features
7.13 10-bit DAC
7.14 UARTs
7.15 SPI serial I/O controller
The DAC allows the LPC2364/65/66/67/68 to generate a variable analog output. The
maximum output value of the DAC is V
The LPC2364/65/66/67/68 each contain four UARTs. In addition to standard transmit and
receive data lines, UART1 also provides a full modem control handshake interface.
The UARTs include a fractional baud rate generator. Standard baud rates such as
115 200 Bd can be achieved with any crystal frequency above 2 MHz.
The LPC2364/65/66/67/68 each contain one SPI controller. SPI is a full duplex serial
interface designed to handle multiple masters and slaves connected to a given bus. Only
a single master and a single slave can communicate on the interface during a given data
transfer. During a data transfer the master always sends 8 bits to 16 bits of data to the
slave, and the slave always sends 8 bits to 16 bits of data to the master.
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10-bit DAC
Resistor string architecture
Buffered output
Power-down mode
Selectable output drive
16 B Receive and Transmit FIFOs.
Register locations conform to 16C550 industry standard.
Receiver FIFO trigger points at 1 B, 4 B, 8 B, and 14 B.
Built-in fractional baud rate generator covering wide range of baud rates without a
need for external crystals of particular values.
Fractional divider for baud rate control, auto baud capabilities and FIFO control
mechanism that enables software flow control implementation.
UART1 equipped with standard modem interface signals. This module also provides
full support for hardware flow control (auto-CTS/RTS).
UART3 includes an IrDA mode to support infrared communication.
Compliant with SPI specification
Synchronous, serial, full duplex communication
Combined SPI master and slave
Maximum data bit rate of one eighth of the input clock rate
8 bits to 16 bits per transfer
Rev. 06 — 1 February 2010
i(VREF)
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LPC2364/65/66/67/68
Single-chip 16-bit/32-bit microcontrollers
© NXP B.V. 2010. All rights reserved.
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