WM8990ECS/RV Wolfson Microelectronics, WM8990ECS/RV Datasheet - Page 145

• Manufacturer Part Number: WM8990ECS/RV
• Description: Audio CODECs Stereo CODEC w.Class AB/D speaker driver
• Manufacturer: Wolfson Microelectronics

Specifications of WM8990ECS/RV

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

w
Production Data
R07 (07h)
Clocking (2)
REGISTER
ADDRESS
8:6
5
4:1
0
15
14
13
12:11
10
9:8
BIT
DCLKDIV
[2:0]
BCLK_DIV
[3:0]
SYSCLK_SRC
CLK_FORCE
MCLK_DIV
[1:0]
MCLK_INV
LABEL
111b
0b
0100b
0b
0b
0b
0b
00b
0b
00b
DEFAULT
Class D Clock Divider
000 = SYSCLK
001 = SYSCLK / 2
010 = SYSCLK / 3
011 = SYSCLK / 4
100 = SYSCLK / 6
101 = SYSCLK / 8
110 = SYSCLK / 12
111 = SYSCLK / 16
Reserved - Do Not Change
BCLK Frequency (Master Mode)
0000 = SYSCLK
0001 = SYSCLK / 1.5
0010 = SYSCLK / 2
0011 = SYSCLK / 3
0100 = SYSCLK / 4
0101 = SYSCLK / 5.5
0110 = SYSCLK / 6
0111 = SYSCLK / 8
1000 = SYSCLK / 11
1001 = SYSCLK / 12
1010 = SYSCLK / 16
1011 = SYSCLK / 22
1100 = SYSCLK / 24
1101 = SYSCLK / 32
1110 = SYSCLK / 44
1111 = SYSCL:K / 48
Reserved - Do Not Change
Reserved - Do Not Change
SYSCLK Source Select
0 = MCLK
1 = PLL output
Forces Clock Source Selection
0 = Existing SYSCLK source (MCLK or PLL output) must be
active when changing to a new clock source.
1 = Allows existing MCLK source to be disabled before
changing to a new clock source.
SYSCLK Pre-divider. Clock source (MCLK or PLL output) will
be divided by this value to generate SYSCLK.
00 = Divide SYSCLK by 1
01 = Reserved
10 = Divide SYSCLK by 2
11 = Reserved
MCLK Invert
0 = Master clock not inverted
1 = Master clock inverted
Reserved - Do Not Change
DESCRIPTION
PD, March 2009, Rev 4.0
WM8990
145