WM8903LGEFK/RV

Manufacturer Part NumberWM8903LGEFK/RV
DescriptionAudio CODECs ULTRA LOW PWR HI FI CODEC
ManufacturerWolfson Microelectronics
WM8903LGEFK/RV datasheets
 


Specifications of WM8903LGEFK/RV

Audio Codec TypeStereo CodecNo. Of Adcs2
No. Of Dacs2No. Of Input Channels6
No. Of Output Channels8Adc / Dac Resolution24bit
Sampling Rate96kHzOperating Temperature Range-40°C To +85°C
Rohs CompliantYesAdcs / Dacs Signal To Noise Ratio96dB
Lead Free Status / RoHS StatusLead free / RoHS Compliant  
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Ultra Low Power CODEC for Portable Audio Applications
DESCRIPTION
The WM8903 is a high performance ultra-low power stereo
CODEC optimised for portable audio applications.
The device features stereo ground-referenced headphone
amplifiers using the Wolfson ‘Class-W’ amplifier techniques
- incorporating an innovative dual-mode charge pump
architecture - to optimise efficiency and power consumption
during playback. The ground-referenced outputs eliminate
headphone coupling capacitors. Both headphone and line
outputs include common mode feedback paths to reject
ground noise.
Control sequences for audio path setup can be pre-loaded
and executed by an integrated sequencer to reduce
software driver development and eliminate pops and clicks
via Wolfson’s SilentSwitch™ technology.
The analogue input stage can be configured for single
ended, pseudo-differential or fully differential inputs. Up to 3
stereo microphone or line inputs may be connected. The
input impedance is constant with PGA gain setting.
A stereo digital microphone interface is provided, which can
also be mixed with the mic/line signals at the output mixers.
A dynamic range controller provides compression and level
control to support a wide range of portable recording
applications. Anti-clip and quick release features offer good
performance in the presence of loud impulsive noises.
Common audio sampling frequencies are supported from a
range of external clocks, including 3MHz, 12MHz or 24MHz.
The WM8903 can operate directly from a single 1.8V
switched supply. For optimal power consumption, the digital
core can be operated from a 1.0V supply.
BLOCK DIAGRAM
WOLFSON MICROELECTRONICS plc
To receive regular email updates, sign up
at
http://www.wolfsonmicro.com/enews
WM8903
FEATURES
4.5mW power consumption for DAC to headphone
playback
DAC SNR 96dB typical, THD -86dB typical
ADC SNR 92dB typical, THD -80dB typical
Control sequencer for pop minimised start-up and shut-
down
Single register write for default start-up sequence
Stereo digital microphone input
3 single ended inputs per stereo channel
2 pseudo differential inputs per stereo channel
1 fully differential mic input per stereo channel
Digital Dynamic Range Controller (compressor / limiter)
Digital sidetone mixing
Ground-referenced headphone driver
Ground-referenced line outputs
Stereo differential line driver for direct interface to WM9001
speaker driver
40-pin 5x5mm QFN package
APPLICATIONS
Portable multimedia players
Multimedia handsets
Handheld gaming
Pre-Production, August 2009, Rev 3.1
Copyright ©2009 Wolfson Microelectronics plc

WM8903LGEFK/RV Summary of contents

  • Page 1

    ... Ground-referenced line outputs • Stereo differential line driver for direct interface to WM9001 speaker driver • 40-pin 5x5mm QFN package APPLICATIONS • Portable multimedia players • Multimedia handsets • Handheld gaming Pre-Production, August 2009, Rev 3.1 Copyright ©2009 Wolfson Microelectronics plc ...

  • Page 2

    WM8903 DESCRIPTION ....................................................................................................... 1 FEATURES............................................................................................................. 1 APPLICATIONS ..................................................................................................... 1 BLOCK DIAGRAM ................................................................................................. 1 TABLE OF CONTENTS ......................................................................................... 2 PIN CONFIGURATION ........................................................................................... 4 ORDERING INFORMATION .................................................................................. 4 PIN DESCRIPTION ................................................................................................ 5 ABSOLUTE MAXIMUM RATINGS ......................................................................... 6 RECOMMENDED OPERATING CONDITIONS ..................................................... 6 ...

  • Page 3

    Pre-Production GENERAL PURPOSE INPUT/OUTPUT (GPIO) .......................................................... 91 INTERRUPTS.............................................................................................................. 96 CONTROL INTERFACE .............................................................................................. 98 CONTROL WRITE SEQUENCER ............................................................................. 100 POWER-ON RESET ................................................................................................. 109 QUICK START-UP AND SHUTDOWN ...................................................................... 111 CHIP RESET AND DEVICE ID .................................................................................. 112 REGISTER MAP ................................................................................................. 113 REGISTER ...

  • Page 4

    ... WM8903 PIN CONFIGURATION ORDERING INFORMATION TEMPERATURE DEVICE RANGE WM8903LGEFK/V -40°C to +85°C WM8903LGEFK/RV -40°C to +85°C Note: Tube quantity = 95 Reel quantity = 3,500 w PACKAGE SENSITIVITY LEVEL 40-lead QFN (5x5x0.55mm, lead-free) 40-lead QFN (5x5x0.55mm, lead-free, tape and reel) Pre-Production MOISTURE PEAK SOLDERING TEMPERATURE MSL3 260° ...

  • Page 5

    Pre-Production PIN DESCRIPTION PIN NAME TYPE 1 DGND Supply Digital Input 2 MCLK 3 GPIO2/ Digital Input/Output DMIC_DAT 4 GPIO1/ Digital Input/Output DMIC_LR 5 INTERRUPT Digital Output 6 BCLK Digital Input/Output 7 DACDAT Digital Input Digital Input/Output 8 LRC Digital ...

  • Page 6

    WM8903 ABSOLUTE MAXIMUM RATINGS Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical Characteristics ...

  • Page 7

    Pre-Production ELECTRICAL CHARACTERISTICS TERMINOLOGY 1. Signal-to-Noise Ratio (dB) – SNR is the difference in level between a full scale output signal and the device output noise with no signal applied, measured over a bandwidth of 20Hz to 20kHz. This ratio ...

  • Page 8

    WM8903 INPUT SIGNAL PATH Single-ended stereo line record - IN1L+IN1R pins to ADC output Test conditions: L_MODE = R_MODE = 00b (Single ended) LIN_VOL = RIN_VOL = 00000b (-1.5dB) Total signal path gain = 4.45dB, incorporating 6dB single-ended to differential ...

  • Page 9

    Pre-Production Single-ended stereo record from analogue microphones - IN2L / IN2R pins to ADC output Test conditions: L_MODE = R_MODE = 00b (Single ended) LIN_VOL = RIN_VOL = 11111b (+28.3dB) Total signal path gain = +34.3dB, incorporating 6dB single-ended to ...

  • Page 10

    WM8903 PGA and microphone boost PARAMETER Minimum PGA gain setting Maximum PGA gain setting Single-ended to differential conversion gain PGA gain accuracy Mute attenuation Equivalent input noise OUTPUT SIGNAL PATH Stereo Playback to Headphones - DAC input to HPOUTL+HPOUTR pins ...

  • Page 11

    Pre-Production Stereo Playback to Line-out - DAC input to LINEOUTL+LINEOUTR pins with 3.01kΩ / 50pF load Test conditions: LINEOUTL_VOL = LINEOUTR_VOL = 111001b (0dB) PARAMETER Full Scale Output Signal Level DC offset Signal to Noise Ratio Total Harmonic Distortion Total ...

  • Page 12

    WM8903 BYPASS PATH Pseudo-differential stereo line input to stereo line output- IN2L-IN3L / IN2R-IN3R pins to LINEOUTL+LINEOUTR pins with 3.01kΩ / 50pF load Test conditions: L_MODE = R_MODE = 01b (Differential Line) LIN_VOL = RIN_VOL = 01111b (+4.2dB) LINEOUTL_VOL = ...

  • Page 13

    Pre-Production CHARGE PUMP PARAMETER Charge pump start-up time External component requirements To achieve specified headphone output power and performance Flyback capacitor (between CFB1 and CFB2 pins) VPOS capacitor VNEG capacitor OTHER PARAMETERS VMID Reference PARAMETER Midrail Reference Voltage (VMID pin) ...

  • Page 14

    WM8903 POWER CONSUMPTION The WM8903 power consumption is dependent on many parameters. Most significantly, it depends on supply voltages, sample rates, mode of operation, and output loading. The power consumption on each supply rail varies approximately with the square of ...

  • Page 15

    Pre-Production Stereo Playback to Headphones - DAC input to HPOUTL+HPOUTR pins with 30Ω load. Test conditions DACBIAS_SEL = 01b (Normal bias x 0.5) DACVMID_BIAS_SEL = 11b (Normal bias x 0.75) PGA_BIAS = 011b (Normal bias x 0.5) CP_DYN_PWR = 1b ...

  • Page 16

    WM8903 SIGNAL TIMING REQUIREMENTS COMMON TEST CONDITIONS Unless otherwise stated, the following test conditions apply throughout the following sections: • • • • Additional, specific test conditions are given within the relevant sections below. MASTER CLOCK Figure 1 Master Clock ...

  • Page 17

    Pre-Production AUDIO INTERFACE MASTER MODE Figure 2 Audio Interface Timing – Master Mode Audio Interface Timing – Master Mode PARAMETER LRC propagation delay from BCLK falling edge ADCDAT propagation delay from BCLK falling edge DACDAT setup time to BCLK rising ...

  • Page 18

    WM8903 SLAVE MODE Figure 3 Audio Interface Timing – Slave Mode Audio Interface Timing – Slave Mode PARAMETER BCLK cycle time BCLK pulse width high BCLK pulse width low LRC set-up time to BCLK rising edge LRC hold time from ...

  • Page 19

    Pre-Production TDM MODE In TDM mode important that two devices to not attempt to drive the ADCDAT pin simultaneously. The timing of the WM8903 ADCDAT pin tri-stating at the start and end of the data transmission is described ...

  • Page 20

    WM8903 DIGITAL FILTER CHARACTERISTICS PARAMETER TEST CONDITIONS ADC Filter Passband Passband Ripple Stopband Stopband Attenuation DAC Normal Filter Passband Passband Ripple Stopband Stopband Attenuation DAC Sloping Stopband Filter Passband Passband Ripple Stopband 1 Stopband 1 Attenuation Stopband 2 Stopband 2 ...

  • Page 21

    Pre-Production DAC FILTER RESPONSES Figure 6 DAC Filter Response for CLK_SYS_MODE = 10b (Clock is 250 x fs related) DAC_SB_FILT = 1b (Sloping StopBand Filter) Sample Rate ≤ 24kHz Figure 8 DAC Filter Response for CLK_SYS_MODE = 10b (Clock is ...

  • Page 22

    WM8903 Figure 10 DAC Filter Response for CLK_SYS_MODE = 01b (Clock is 272 x fs related) DAC_SB_FILT = 0b (Normal Filter) Sample Rate = 88.2kHz ADC FILTER RESPONSES Figure 11 ADC Filter Response for CLK_SYS_MODE = 10b (not applicable to ...

  • Page 23

    Pre-Production Figure 13 ADC Filter Passband Ripple for CLK_SYS_MODE = 10b ADC HIGH PASS FILTER RESPONSES 2.1246m -1.1717 -2.3455 -3.5193 -4.6931 -5.8669 -7.0407 -8.2145 -9.3883 -10.562 -11.736 1 2.6923 7.2484 19.515 52.54 141.45 380.83 MAGNITUDE(dB) Figure 14 ADC Digital High ...

  • Page 24

    WM8903 DE-EMPHASIS FILTER RESPONSES MAGNITUDE(dB 5000 10000 - -10 Frequency (Hz) Figure 16 De-Emphasis Digital Filter Response (32kHz) MAGNITUDE(dB 5000 10000 15000 - ...

  • Page 25

    Pre-Production DEVICE DESCRIPTION ANALOGUE INPUT SIGNAL PATH The WM8903 has six analogue input pins, which may be used to support connections to multiple microphone or line input sources. The input multiplexer on the Left and Right channels can be used ...

  • Page 26

    WM8903 INPUT PGA ENABLE The input PGAs (Programmable Gain Amplifiers) and Multiplexers are enabled using register bits INL_ENA and INR_ENA, as shown in Table 1. REGISTER ADDRESS R12 (0Ch) Power Management 0 Table 1 Input PGA Enable To enable the ...

  • Page 27

    Pre-Production REGISTER ADDRESS R46 (2Eh) Analogue Left Input 1 R47 (2Fh) Analogue Right Input 1 Table 2 Input PGA Mode Selection w BIT LABEL DEFAULT 5:4 L_IP_SEL_N 00 [1:0] 3:2 L_IP_SEL_P 01 [1:0] 1:0 L_MODE [1:0] 00 5:4 R_IP_SEL_N 00 ...

  • Page 28

    WM8903 SINGLE-ENDED INPUT The Single-Ended PGA configuration is illustrated in Figure 23 for the Left channel. The available gain in this mode is from -1.57dB to +28.5dB in non-linear steps. The input impedance is 12kΩ. The input to the ADC ...

  • Page 29

    Pre-Production DIFFERENTIAL MICROPHONE INPUT The Differential Mic PGA configuration is illustrated in Figure 25 for the Left channel. The available gain in this mode is from +12dB to +30dB in 3dB linear steps. The input impedance is 120kΩ. In this ...

  • Page 30

    WM8903 LIN_VOL[4:0], RIN_VOL[4:0] Table 4 Input PGA Volume Range w GAIN – PGA MODE = 00000 -1.5 dB 00001 -1.3 dB 00010 -1.0 dB 00011 -0.7 dB 00100 -0.3 dB 00101 0.0 dB 00110 +0.3 dB 00111 ...

  • Page 31

    Pre-Production INPUT PGA COMMON MODE AMPLIFIER In Differential Line Mode only, a Common Mode amplifier can be enabled as part of the input PGA circuit. This feature provides approximately 20dB reduction in common mode noise on the differential input, which ...

  • Page 32

    WM8903 ELECTRET CONDENSER MICROPHONE INTERFACE Electret Condenser microphones may be connected as single-ended or differential inputs to the Input PGAs described in the “Analogue Input Signal Path” section. The WM8903 provides a low-noise reference voltage suitable for biasing electret condenser ...

  • Page 33

    Pre-Production MICROPHONE INSERTION / REMOVAL DETECTION In a typical application, microphone insertion would be detected when the MICBIAS current exceeds the Current Detect threshold set by MICDET_THR. In order to generate a MICBIAS Current Detect interrupt from this event, MICDET_INV ...

  • Page 34

    WM8903 MICROPHONE HOOK SWITCH DETECTION In a typical application, microphone hook switch operation would be detected when the MICBIAS current exceeds the Short Circuit Detect threshold set by MICSHORT_THR. In order to generate a MICBIAS Short Circuit Detect interrupt from ...

  • Page 35

    Pre-Production MICROPHONE HOOK SWITCH CLOCKING REQUIREMENTS A clock is required for the Hook Switch Detect circuit. This requires Any hook switch press (or release) which happens while one or more of the above criteria are not satisfied ...

  • Page 36

    WM8903 Figure 29 Digital Microphone Interface Timing The digital microphone interface control fields are described in Table 7. REGISTER ADDRESS R164 (A4h) Clock Rate Test 4 Table 7 Digital Microphone Interface Control In addition to setting the ADC_DIG_MIC bit as ...

  • Page 37

    Pre-Production ANALOGUE-TO-DIGITAL CONVERTER (ADC) The WM8903 uses two 24-bit, 64x oversampled sigma-delta ADCs. The use of multi-bit feedback and high oversampling rates reduces the effects of jitter and high frequency noise. The ADC full-scale input level is proportional to AVDD. ...

  • Page 38

    WM8903 ADCL_VOL or ADCR_VOL Volume (dB) 0h MUTE 1h -71.625 2h -71.250 3h -70.875 4h -70.500 5h -70.125 6h -69.750 7h -69.375 8h -69.000 9h -68.625 Ah -68.250 Bh -67.875 Ch -67.500 Dh -67.125 Eh -66.750 Fh -66.375 10h -66.000 ...

  • Page 39

    Pre-Production HIGH-PASS FILTER (HPF) A digital high-pass filter is applied by default to the ADC path to remove DC offsets. This filter can also be programmed to remove low frequency noise in handheld applications (e.g. wind noise, handling noise or ...

  • Page 40

    WM8903 ADC OVERSAMPLING RATIO (OSR) The ADC oversampling rate is programmable to allow power consumption versus audio performance trade-offs. The default oversampling rate is high for best performance; using the lower OSR setting reduces ADC power consumption. REGISTER ADDRESS R10 ...

  • Page 41

    Pre-Production Figure 30 DRC Compression Characteristic The slope of R0 and R1 are determined by register fields DRC_R0_SLOPE_COMP and DRC_R1_SLOPE_COMP respectively. A slope of 1 indicates constant gain in this region. A slope less than 1 represents compression (i.e. a ...

  • Page 42

    WM8903 REGISTER ADDRESS R42 (2Ah) DRC 2 R43 (2Bh) DRC 3 Table 15 DRC Compression Control GAIN LIMITS The minimum and maximum gain applied by the DRC is set by register fields DRC_MINGAIN and DRC_MAXGAIN. These limits can be used ...

  • Page 43

    Pre-Production REGISTER ADDRESS R41(29h) DRC 1 Table 16 DRC Gain Limits DYNAMIC CHARACTERISTICS The dynamic behaviour determines how quickly the DRC responds to changing signal levels. Note that the DRC responds to the average (RMS) signal amplitude over a period ...

  • Page 44

    WM8903 ANTI-CLIP CONTROL The DRC includes an Anti-Clip feature to avoid signal clipping when the input amplitude rises very quickly. This feature uses a feed-forward technique for early detection of a rising signal level. Signal clipping is avoided by dynamically ...

  • Page 45

    Pre-Production REGISTER ADDRESS R40 (28h) DRC 0 R41 (29h) DRC 1 Table 19 DRC Quick-Release Control GAIN SMOOTHING The DRC includes a gain smoothing filter in order to prevent gain ripples. A programmable level of hysteresis is also used to ...

  • Page 46

    WM8903 INITIALISATION When the DRC is initialised, the gain is set to the level determined by the DRC_STARTUP_GAIN register field. The default setting is 0dB, but values from -18dB to +36dB are available, as described in Table 21. REGISTER ADDRESS ...

  • Page 47

    Pre-Production Figure 31 Digital Mixing Paths The polarity of each ADC output signal can be changed under software control using the ADCL_DATINV and ADCR_DATINV register bits. The AIFADCL_SRC and AIFADCR_SRC register bits may be used to select which ADC is ...

  • Page 48

    WM8903 REGISTER ADDRESS R24 (18h) Audio Interface 0 R38 (26h) ADC Digital 0 Table 22 Digital Mixing Control w BIT LABEL DEFAULT 12 DACL_DATINV 0 11 DACR_DATINV 0 AIFADCL_SRC AIFADCR_SRC 1 5 AIFDACL_SRC 0 4 AIFDACR_SRC 1 ...

  • Page 49

    Pre-Production DAC INTERFACE VOLUME BOOST A digital gain function is available at the audio interface to boost the DAC volume when a small signal is received on DACDAT. This is controlled using register bits DAC_BOOST[1:0]. To prevent clipping at the ...

  • Page 50

    WM8903 ADCL_DAC_SVOL or ADCR_DAC_SVOL Table 25 Digital Sidetone Volume SIDETONE VOLUME 0000 -36 0001 -33 0010 -30 0011 -27 0100 -24 0101 -21 0110 -18 0111 -15 1000 -12 1001 -9 1010 -6 1011 -3 1100 0 ...

  • Page 51

    Pre-Production DIGITAL-TO-ANALOGUE CONVERTER (DAC) The WM8903 DACs receive digital input data from the DACDAT pin and via the digital sidetone path (see “Digital Mixing” section). The digital audio data is converted to oversampled bit streams in the on-chip, true 24-bit ...

  • Page 52

    WM8903 DACL_VOL or DACR_VOL Volume (dB) 0h MUTE 1h -71.625 2h -71.250 3h -70.875 4h -70.500 5h -70.125 6h -69.750 7h -69.375 8h -69.000 9h -68.625 Ah -68.250 Bh -67.875 Ch -67.500 Dh -67.125 Eh -66.750 Fh -66.375 10h -66.000 ...

  • Page 53

    Pre-Production DAC SOFT MUTE AND SOFT UN-MUTE The WM8903 has a soft mute function. When enabled, this gradually attenuates the volume of the DAC output. When soft mute is disabled, the gain will either gradually ramp back up to the ...

  • Page 54

    WM8903 DAC MONO MIX A DAC digital mono-mix mode can be enabled using the DAC_MONO register bit. This mono mix will be output on whichever DAC is enabled. To prevent clipping, a -6dB attenuation is automatically applied to the mono ...

  • Page 55

    Pre-Production DAC BIAS CONTROL The analogue circuits within the DAC use the Master bias current (see “Reference Voltages and Master Bias”). The DAC bias currents can also be reduced using the DACBIAS_SEL and DACVMID_SEL fields as described in Table 33. ...

  • Page 56

    WM8903 OUTPUT SIGNAL PATH The WM8903 has one pair of analogue mixers (the “left” and right” mixers) feeding the headphone outputs HPOUTL and HPOUTR as well as the line outputs LINEOUTL and LINEOUTR, and a separate pair of mixers (the ...

  • Page 57

    Pre-Production OUTPUT SIGNAL PATHS ENABLE Each output pin and each mixer can be independently enabled and disabled as shown in Table 35. Note that the Headphone Outputs and Line Outputs are also controlled by fields located within Register R90 and ...

  • Page 58

    WM8903 OUTPUT PGA BIAS CONTROL The output PGA circuits use the Master bias current (see “Reference Voltages and Master Bias”). The output PGA bias currents can also be controlled using the PGA_BIAS field as described in Table 36. Selecting a ...

  • Page 59

    Pre-Production OUTPUT MIXER CONTROL Each of the four output mixers has the same four inputs: • DAC Left • DAC Right • Bypass Left • Bypass Right The input signals to the left and right mixers (feeding HPOUTL/R and LINEOUTL/R) ...

  • Page 60

    WM8903 The input signals to the speaker mixers are enabled and controlled using the register fields described in Table 39. These mixers provide a selectable 0dB or -6dB volume control on each input. The input signals may also be controlled ...

  • Page 61

    Pre-Production REGISTER ADDRESS R55 (37h) Analogue Spk Mix Right 1 Table 39 Speaker Mixer Control OUTPUT VOLUME CONTROL Each analogue output can be independently controlled. The headphone output control fields are described in Table 40. The line output control fields ...

  • Page 62

    WM8903 REGISTER ADDRESS R57 (39h) Analogue OUT1 Left R58 (3Ah) Analogue OUT1 Right Table 40 Volume Control for HPOUTL and HPOUTR w BIT LABEL DEFAULT 8 HPL_MUTE 0 7 HPOUTVU 0 HPOUTLZC 6 0 5:0 HPOUTL_VOL 10_1101 [5:0] HPR_MUTE 8 ...

  • Page 63

    Pre-Production REGISTER ADDRESS R59 (3Bh) Analogue OUT2 Left R60 (3Ch) Analogue OUT2 Right Table 41 Volume Control for LINEOUTL and LINEOUTR w BIT LABEL DEFAULT 8 LINEOUTL_MUTE 0 7 LINEOUTVU 0 LINEOUTLZC 6 0 5:0 LINEOUTL_VOL 11_1001 [5:0] 8 LINEOUTR_MUT ...

  • Page 64

    WM8903 REGISTER ADDRESS R62 (3Eh) Analogue OUT3 Left R63 (3Fh) Analogue OUT3 Right Table 42 Volume Control for LON/LOP and RON/ROP w BIT LABEL DEFAULT 8 SPKL_MUTE 1 7 SPKVU 0 SPKLZC 6 0 5:0 SPKL_VOL [5:0] 11_1001 8 SPKR_MUTE ...

  • Page 65

    Pre-Production ANALOGUE OUTPUTS The WM8903 has eight analogue output pins: • Headphone outputs, HPOUTL and HPOUTR • Line outputs, LINEOUTL and LINEOUTR • Differential line outputs, LON/LOP and RON/ROP The output signal paths and associated control registers are illustrated in ...

  • Page 66

    WM8903 EXTERNAL COMPONENTS FOR GROUND-REFERENCED OUTPUTS In the case of the ground referenced outputs HPOUTL, HPOUTR, LINEOUTL and LINEOUTR recommended to connect a zobel network to the audio output pins for best audio performance in all applications. The ...

  • Page 67

    Pre-Production REFERENCE VOLTAGES AND MASTER BIAS This section describes the analogue reference voltage and bias current controls. It also describes the VMID soft-start circuit for pop-free start-up and shut-down. Note that, under the recommended usage conditions of the WM8903, these ...

  • Page 68

    WM8903 A pop-suppressed start-up requires VMID to be enabled smoothly, without the step change normally associated with the initial stage of the VMID capacitor charging. A pop-suppressed start-up also requires the analogue bias current to be enabled throughout the signal ...

  • Page 69

    Pre-Production POP SUPPRESSION CONTROL The WM8903 incorporates Wolfson’s SilentSwitch™ technology which enables pops normally associated with Start-Up, Shut-Down or signal path control to be suppressed. To achieve maximum benefit from these features, careful attention is required to the sequence and ...

  • Page 70

    WM8903 The register bits relating to pop suppression control are defined in Table 47. REGISTER ADDRESS R5 (05h) VMID Control 0 R65 (41h) R90 (5Ah) Analogue BIT LABEL DEFAULT 7 VMID_TIE_ENA 0 6 BUFIO_ENA 0 0 VMID_BUF_ENA ...

  • Page 71

    Pre-Production REGISTER ADDRESS R94 (5Eh) Analogue Lineout 0 Table 47 Pop Suppression Control w BIT LABEL DEFAULT 7 LINEOUTL_RMV 0 _SHORT LINEOUTL_ENA_ 6 0 OUTP 5 LINEOUTL_ENA_ 0 DLY LINEOUTL_ENA LINEOUTR_RMV 0 _SHORT 2 LINEOUTR_ENA 0 _OUTP ...

  • Page 72

    WM8903 CHARGE PUMP The WM8903 incorporates a dual-mode Charge Pump which generates the supply rails for the headphone and line output drivers (LINEOUTL/R). The Charge Pump has a single supply input, CPVDD, and generates split rails VPOS and VNEG according ...

  • Page 73

    Pre-Production For example, with MCLKDIV2=0 256fs gives a charge pump clock division ratio of 12, hence • • 128fs gives a charge pump clock division ratio of 6, hence • • CHARGE PUMP REGISTERS The Charge Pump control fields are ...

  • Page 74

    WM8903 If periodic updates to the DC offset correction is required, then DCS_MODE should be modified. Setting this field to 11b selects START_UPDATE servo mode, which causes the DC offset to be measured and corrected on a periodic basis. The ...

  • Page 75

    Pre-Production REGISTER ADDRESS R71 (47h) DC Servo 4 R72 (48h) DC Servo 5 R73 (49h) DC Servo 6 R74 (4Ah) DC Servo 7 R81 (51h) DC Servo Readback 1 R82 (52h) DC Servo Readback 2 R83 (53h) DC Servo Readback ...

  • Page 76

    WM8903 DIGITAL AUDIO INTERFACE The digital audio interface is used for inputting DAC data into the WM8903 and outputting ADC data from it. It uses four pins: • ADCDAT: ADC data output • DACDAT: DAC data input • LRC: DAC ...

  • Page 77

    Pre-Production BCLK_DIV and LRCLK_RATE are defined in Table 52. The clocking scheme is illustrated in the “Clocking and Sample Rates” section - see Figure 54. REGISTER ADDRESS R26 (1Ah) Audio Interface 2 R27 (1Bh) Audio Interface 3 Table 52 Digital ...

  • Page 78

    WM8903 The register bits controlling audio data format and word length are summarised in Table 53. REGISTER ADDRESS R25 (19h) Audio Interface 1 Table 53 Audio Data Format Control In Left Justified mode, the MSB is available on the first ...

  • Page 79

    Pre-Production In Right Justified mode, the LSB is available on the last rising edge of BCLK before a LRCLK transition. All other bits are transmitted before (MSB first). Depending on word length, BCLK frequency and sample rate, there may be ...

  • Page 80

    WM8903 Figure 41 DSP/PCM Mode Audio Interface (mode A, AIF_LRCLK_INV=0, Master) Figure 42 DSP/PCM Mode Audio Interface (mode B, AIF_LRCLK_INV=1, Master) Figure 43 DSP/PCM Mode Audio Interface (mode A, AIF_LRCLK_INV=0, Slave) w Pre-Production PP, Rev 3.1, August 2009 80 ...

  • Page 81

    Pre-Production Figure 44 DSP/PCM Mode Audio Interface (mode B, AIF_LRCLK_INV=0, Slave) TIME DIVISION MULTIPLEXING (TDM) TDM allows more than two devices to share a single digital audio bus, as shown below. Figure 45 TDM with WM8903 as Master w BCLK ...

  • Page 82

    WM8903 WM8903 Third audio device Figure 46 TDM with Third Audio Device as Master The WM8903 supports TDM in master and slave modes, for both incoming and outgoing audio data, in all data formats and word lengths. When TDM is ...

  • Page 83

    Pre-Production When TDM is enabled, BCLK frequency must be high enough to allow data from both time slots to be transferred. The relative timing of Slot 0 and Slot 1 depends upon the selected data format as shown in Figure ...

  • Page 84

    WM8903 Figure 50 TDM in DSP Mode A LRC BCLK ADCDAT / DACDAT Figure 51 TDM in DSP Mode B COMPANDING The WM8903 supports A-law and μ-law companding on both transmit (ADC) and receive (DAC) sides as shown in Table ...

  • Page 85

    Pre-Production Companding uses a piecewise linear approximation of the following equations (as set out by ITU-T G.711 standard) for data compression: μ-law (where μ=255 for the U.S. and Japan): A-law (where A=87.6 for Europe): F( ...

  • Page 86

    WM8903 The companded data is also inverted as recommended by the G.711 standard (all 8 bits are inverted for μ-law, all even data bits are inverted for A-law). Companded data is transmitted in the first 8 MSBs of its respective ...

  • Page 87

    Pre-Production CLOCKING AND SAMPLE RATES The WM8903 supports a wide range of standard audio sample rates from 8kHz to 96kHz. When the DAC and ADC are both enabled, they operate at the same sample rate, f Note that the 88.2kHz ...

  • Page 88

    WM8903 CONTROL INTERFACE CLOCKING In certain configurations, such as analog bypass to differential line outputs, WM8903 can be used without MCLK (compared to LINEOUTL/R, which requires the charge pump hence requires MCLK). Without MCLK applied, CLK_SYS_ENA should be left in ...

  • Page 89

    Pre-Production CLOCKING REGISTERS The WM8903 clocking is configured using the register bits defined in Table 61. REGISTER ADDRESS R20 (14h) Clock Rates 0 R21 (15h) Clock Rates 1 R22 (16h) Clock Rates 2 Table 61 Clocking Control w BIT LABEL ...

  • Page 90

    WM8903 1010 to 1111 Table 62 Sample Rate Decoder Control The clock division ratios available with CLK_SYS_MODE = 00 are suitable for use with standard audio master clocks. For example, with a 12.288MHz CLK_SYS and 48kHz sample rate, the CLK_SYS ...

  • Page 91

    Pre-Production GENERAL PURPOSE INPUT/OUTPUT (GPIO) The WM8903 provides five multi-function pins which can be configured to provide a number of different functions. These are digital input/output pins on the DBVDD power domain. The GPIO pins are: • GPIO1/DMIC_LR • GPIO2/DMIC_DAT ...

  • Page 92

    WM8903 BCLK is the default function of GPIO5. This may be input or output. Note that, when BCLK is enabled on this pin (GP5_FN = 1h), the other GPIO control fields for this pin have no effect. When BCLK is ...

  • Page 93

    Pre-Production REGISTER ADDRESS R118 (76h) GPIO Control 3 w BIT LABEL DEFAULT 6 GP2_OP_CFG 0 GP2_IP_CFG GP2_LVL 0 3 GP2_PD 1 2 GP2_PU 0 1 GP2_INTMODE 0 GP2_DB 0 0 13:8 GP3_FN[5:0] 00_0000 7 GP3_DIR 1 6 ...

  • Page 94

    WM8903 REGISTER ADDRESS R119 (77h) GPIO Control 4 R120 (78h) GPIO Control 5 w BIT LABEL DEFAULT 0 GP3_DB 0 13:8 GP4_FN[5:0] 00_0010 7 GP4_DIR 0 6 GP4_OP_CFG 0 GP4_IP_CFG 5 1 GP4_LVL GP4_PD 0 2 GP4_PU ...

  • Page 95

    Pre-Production REGISTER ADDRESS Table 65 GPIO Control w BIT LABEL DEFAULT 4 GP5_LVL 0 GP5_PD GP5_PU 0 1 GP5_INTMODE 0 0 GP5_DB 0 WM8903 DESCRIPTION GPIO Output Level (when GP5_FN = 00000 Logic 0 1 ...

  • Page 96

    WM8903 INTERRUPTS The Interrupt Controller has multiple inputs. These include the GPIO input pins and the MICBIAS current detection circuits. Any combination of these inputs can be used to trigger an Interrupt (IRQ) event. There is an Interrupt Status field ...

  • Page 97

    Pre-Production REGISTER ADDRESS R121 (79h) Interrupt Status 1 R122 (7Ah) Interrupt Status 1 Mask w BIT LABEL DEFAULT 15 MICSHRT_EINT 0 MICDET_EINT 14 0 WSEQ_BUSY_E 13 0 INT 4 GP5_EINT 0 3 GP4_EINT 0 2 GP3_EINT 0 GP2_EINT 1 0 ...

  • Page 98

    WM8903 REGISTER ADDRESS R123 (7Bh) Interrupt Polarity 1 R126 (7Eh) Interrupt Control Table 66 Interrupt Control CONTROL INTERFACE The WM8903 is controlled by writing to registers through a 2-wire serial control interface. A control word consists of 24 bits, transmitted ...

  • Page 99

    Pre-Production The WM8903 supports the following read and write operations: • • • • The data format for these operations is shown below Terminology used in the following figures: TERMINOLOGY Table 68 Control Interface Terminology Figure 56 Single Write Figure ...

  • Page 100

    WM8903 CONTROL WRITE SEQUENCER The Control Write Sequencer is a programmable unit that forms part of the WM8903 control interface logic. It provides the ability to perform a sequence of register write operations with the minimum of demands on the ...

  • Page 101

    Pre-Production REGISTER ADDRESS R108 (6Ch) Write Sequencer 0 R111 (6Fh) Write Sequencer 3 R112 (70h) Write Sequencer 4 Table 69 Write Sequencer Control – Initiating a Sequence PROGRAMMING A SEQUENCE A sequence consists of write operations to data bits (or ...

  • Page 102

    WM8903 WSEQ_DATA_START is a 4-bit field which identifies the LSB position within the selected Control Register to which the data should be written. Setting WSEQ_DATA_START = 0100 will cause 1-bit data to be written to bit 4. With this setting, ...

  • Page 103

    Pre-Production REGISTER ADDRESS R108 (6Ch) Write Sequencer 0 R109 (6Dh) Write Sequencer 1 R110 (6Eh) Write Sequencer 2 Table 70 Write Sequencer Control - Programming a Sequence In summary, the Control Register to be written is set by the WSEQ_ADDR ...

  • Page 104

    WM8903 Figure 60 Control Write Sequencer Example DEFAULT SEQUENCES When the WM8903 is powered up, two Control Write Sequences are available through ROM/default settings. The purpose of these sequences, and the register write required to initiate them is summarised in ...

  • Page 105

    Pre-Production WSEQ REGISTER WIDTH INDEX ADDRESS 0 R4 (4h) 5 bits 1 R65 (41h) 1 bit 2 R17 (11h) 2 bits 3 R65 (41h) 1 bit 4 R5 (5h) 8 bits 5 R17 (11h) 2 bits 6 R5 (5h) 2 ...

  • Page 106

    WM8903 WSEQ REGISTER WIDTH INDEX ADDRESS 19 R94 (5Eh) 8 bits 20 R90 (5Ah) 8 bits 21 R94 (5Eh) 8 bits 22 R69 (45h) 2 bits 23 R67 (43h) 4 bits 24 R67 (43h) 4 bits 25 R255 (FFh) 1 ...

  • Page 107

    Pre-Production WSEQ REGISTER WIDTH INDEX ADDRESS 28 R90 (5Ah) 8 bits 29 R94 (5Eh) 8 bits 30 R255 (FFh) 1 bit 31 R255 (FFh) 1 bit 32 R94 (5Eh) 8 bits 33 R90 (5Ah) 8 bits 34 R90 (5Ah) 8 ...

  • Page 108

    WM8903 WSEQ REGISTER WIDTH INDEX ADDRESS 37 R98 (62h) 1 bit 38 R18 (12h) 2 bits 39 R22 (16h) 1 bit 40 R14 (0Eh) 2 bits 41 R15 (0Fh) 2 bits 42 R13 (0Dh) 2 bits 43 R4 (04h) 1 ...

  • Page 109

    Pre-Production POWER-ON RESET Figure 61 Internal Power on Reset Circuit Schematic The WM8903 includes an internal Power-On-Reset Circuit, as shown in Figure 61, which is used to reset the digital logic into a default state after power up. The POR ...

  • Page 110

    WM8903 POWER-UP TIMING - DCVDD POWERED BEFORE AVDD Figure 63 Typical Power up Sequence where DCVDD is Powered before AVDD Figure 63 shows the power-up sequence where DCVDD is powered up before AVDD assumed that DCVDD is at ...

  • Page 111

    Pre-Production QUICK START-UP AND SHUTDOWN The WM8903 has the capability to perform a quick start-up and shut-down with a minimum number of register operations. The Control Write Sequencer is configured with default start-up settings that configure the device for DAC ...

  • Page 112

    WM8903 CHIP RESET AND DEVICE ID The WM8903 can be reset by writing to Register 0. This is a read-only register field, and the contents will not be affected by writing to this Register. The Device ID can be read ...

  • Page 113

    Pre-Production REGISTER MAP The complete register map is shown below. The detailed description can be found in the relevant text of the device description. The WM8903 can be configured using the Control Interface. REG NAME (0h) ...

  • Page 114

    WM8903 REG NAME (1Ah) Interface 2 R27 Audio (1Bh) Interface 3 R30 DAC Digital (1Eh) Volume Left R31 (1Fh) DAC Digital Volume Right R32 (20h) DAC Digital 0 ...

  • Page 115

    Pre-Production REG NAME Right 1 R57 (39h) Analogue OUT1 Left R58 Analogue (3Ah) OUT1 Right R59 Analogue (3Bh) OUT2 Left R60 Analogue (3Ch) OUT2 Right ...

  • Page 116

    WM8903 REG NAME R112 Write (70h) Sequencer 4 R116 GPIO 0 0 (74h) Control 1 R117 GPIO 0 0 (75h) Control 2 R118 GPIO 0 0 (76h) Control 3 R119 GPIO 0 0 (77h) ...

  • Page 117

    Pre-Production REGISTER BITS BY ADDRESS REGISTER BIT LABEL ADDRESS R0 (00h) 15:0 SW_RST_DEV_ID1[15:0] 1000_1001_0000_0011 Writing to this register resets all SW Reset and ID Register 00h SW Reset and ID REGISTER BIT LABEL ADDRESS R1 (01h) 3:0 CHIP_REV[3:0] Revision Number ...

  • Page 118

    WM8903 REGISTER BIT LABEL ADDRESS R5 (05h) 7 VMID_TIE_ENA VMID Control 0 6 BUFIO_ENA 5 VMID_IO_ENA 4:3 VMID_SOFT[1:0] 2:1 VMID_RES[1:0] 0 VMID_BUF_ENA Register 05h VMID Control 0 REGISTER BIT LABEL ADDRESS R6 (06h) Mic 7:6 Reserved Bias Control 0 5:4 ...

  • Page 119

    Pre-Production REGISTER BIT LABEL ADDRESS R8 (08h) 5 DAC_BIAS_BOOST Analogue DAC 0 4:3 DACBIAS_SEL[1:0] 2:1 DACVMID_BIAS_SEL[1:0] Register 08h Analogue DAC 0 REGISTER BIT LABEL ADDRESS R10 (0Ah) 0 ADC_OSR128 Analogue ADC 0 Register 10h Analogue ADC 0 REGISTER BIT LABEL ...

  • Page 120

    WM8903 REGISTER BIT LABEL ADDRESS R14 (0Eh) 1 HPL_PGA_ENA Power Management 2 0 HPR_PGA_ENA Register 0Eh Power Management 2 REGISTER BIT LABEL ADDRESS R15 (0Fh) 1 LINEOUTL_PGA_ENA Power Management 3 0 LINEOUTR_PGA_ENA Register 0Fh Power Management 3 REGISTER BIT LABEL ...

  • Page 121

    Pre-Production REGISTER BIT LABEL ADDRESS R18 (12h) 3 DACL_ENA Power Management 6 2 DACR_ENA 1 ADCL_ENA 0 ADCR_ENA Register 12h Power Management 6 REGISTER BIT LABEL ADDRESS R20 (14h) 0 MCLKDIV2 Clock Rates 0 Register 14h Clock Rates 0 REGISTER ...

  • Page 122

    WM8903 REGISTER BIT LABEL ADDRESS 9:8 CLK_SYS_MODE[1:0] 3:0 SAMPLE_RATE[3:0] Register 15h Clock Rates 1 REGISTER BIT LABEL ADDRESS R22 (16h) 2 CLK_SYS_ENA Clock Rates 2 1 CLK_DSP_ENA 0 TO_ENA Register 16h Clock Rates 2 w DEFAULT DESCRIPTION 1010 to 1111 ...

  • Page 123

    Pre-Production REGISTER BIT LABEL ADDRESS R24 (18h) 12 DACL_DATINV Audio Interface 0 11 DACR_DATINV 10:9 DAC_BOOST[1:0] 8 LOOPBACK 7 AIFADCL_SRC 6 AIFADCR_SRC 5 AIFDACL_SRC 4 AIFDACR_SRC 3 ADC_COMP 2 ADC_COMPMODE 1 DAC_COMP 0 DAC_COMPMODE Register 18h Audio Interface 0 w ...

  • Page 124

    WM8903 REGISTER BIT LABEL ADDRESS R25 (19h) 13 AIFDAC_TDM Audio Interface 1 12 AIFDAC_TDM_CHAN 11 AIFADC_TDM 10 AIFADC_TDM_CHAN 9 LRCLK_DIR 7 AIF_BCLK_INV 6 BCLK_DIR 4 AIF_LRCLK_INV 3:2 AIF_WL[1:0] 1:0 AIF_FMT[1:0] Register 19h Audio Interface 1 w DEFAULT DESCRIPTION DAC TDM ...

  • Page 125

    Pre-Production REGISTER BIT LABEL ADDRESS R26 (1Ah) 4:0 BCLK_DIV[4:0] Audio Interface 2 Register 1Ah Audio Interface 2 REGISTER BIT LABEL ADDRESS R27 (1Bh) 10:0 LRCLK_RATE[10:0] 000_0010_0010 LRC Rate (Master Mode) Audio Interface 3 Register 1Bh Audio Interface 3 REGISTER BIT ...

  • Page 126

    WM8903 REGISTER BIT LABEL ADDRESS R31 (1Fh) 8 DACVU DAC Digital Volume Right 7:0 DACR_VOL[7:0] 1100_0000 Right DAC Digital Volume Register 1Fh DAC Digital Volume Right REGISTER BIT LABEL ADDRESS R32 (20h) 11:8 ADCL_DAC_SVOL[3:0] DAC Digital 0 7:4 ADCR_DAC_SVOL[3:0] 3:2 ...

  • Page 127

    Pre-Production REGISTER BIT LABEL ADDRESS R33 (21h) 12 DAC_MONO DAC Digital 1 11 DAC_SB_FILT 10 DAC_MUTERATE 9 DAC_MUTEMODE 3 DAC_MUTE 2:1 DEEMPH[1:0] 0 DAC_OSR Register 21h DAC Digital 1 REGISTER BIT LABEL ADDRESS R36 (24h) 8 ADCVU ADC Digital Volume ...

  • Page 128

    WM8903 REGISTER BIT LABEL ADDRESS R37 (25h) 8 ADCVU ADC Digital Volume Right 7:0 ADCR_VOL[7:0] 1100_0000 Right ADC Digital Volume Register 25h ADC Digital Volume Right REGISTER BIT LABEL ADDRESS R38 (26h) 6:5 ADC_HPF_CUT[1:0] ADC Digital 0 4 ADC_HPF_ENA 1 ...

  • Page 129

    Pre-Production REGISTER BIT LABEL ADDRESS R40 (28h) 15 DRC_ENA DRC 0 12:11 DRC_THRESH_HYST[1:0] 10:6 DRC_STARTUP_GAIN[4:0] 5 DRC_FF_DELAY 3 DRC_SMOOTH_ENA 2 DRC_QR_ENA 1 DRC_ANTICLIP_ENA 0 DRC_HYST_ENA Register 28h DRC 0 w DEFAULT DESCRIPTION DRC enable enabled 0 = ...

  • Page 130

    WM8903 REGISTER BIT LABEL ADDRESS R41 (29h) 15:12 DRC_ATTACK_RATE[3:0] DRC 1 11:8 DRC_DECAY_RATE[3:0] 7:6 DRC_THRESH_QR[1:0] 5:4 DRC_RATE_QR[1:0] 3:2 DRC_MINGAIN[1:0] 1:0 DRC_MAXGAIN[1:0] Register 29h DRC 1 w DEFAULT DESCRIPTION Gain attack rate (seconds/6dB) 0011 0000 = instantaneous 0001 = 363us 0010 ...

  • Page 131

    Pre-Production REGISTER BIT LABEL ADDRESS R42 (2Ah) 5:3 DRC_R0_SLOPE_COMP[2:0] DRC 2 2:0 DRC_R1_SLOPE_COMP[2:0] Register 2Ah DRC 2 REGISTER BIT LABEL ADDRESS R43 (2Bh) 10:5 DRC_THRESH_COMP[5:0] DRC 3 4:0 DRC_AMP_COMP[4:0] Register 2Bh DRC 3 w DEFAULT DESCRIPTION Compressor slope R0 100 ...

  • Page 132

    WM8903 REGISTER BIT LABEL ADDRESS R44 (2Ch) 7 LINMUTE Analogue Left Input 0 4:0 LIN_VOL[4:0] Register 2Ch Analogue Left Input 0 w DEFAULT DESCRIPTION Left Input PGA Mute not muted 1 = muted 0_0101 Left Input PGA ...

  • Page 133

    Pre-Production REGISTER BIT LABEL ADDRESS R45 (2Dh) 7 RINMUTE Analogue Right Input 0 4:0 RIN_VOL[4:0] Register 2Dh Analogue Right Input 0 w DEFAULT DESCRIPTION Right Input PGA Mute not muted 1 = muted 0_0101 Right Input PGA ...

  • Page 134

    WM8903 REGISTER BIT LABEL ADDRESS R46 (2Eh) 6 INL_CM_ENA Analogue Left Input 1 5:4 L_IP_SEL_N[1:0] 3:2 L_IP_SEL_P[1:0] 1:0 L_MODE[1:0] Register 2Eh Analogue Left Input 1 REGISTER BIT LABEL ADDRESS R47 (2Fh) 6 INR_CM_ENA Analogue Right Input 1 5:4 R_IP_SEL_N[1:0] 3:2 ...

  • Page 135

    Pre-Production REGISTER BIT LABEL ADDRESS R50 (32h) 3 DACL_TO_MIXOUTL Analogue Left Mix 0 2 DACR_TO_MIXOUTL 1 BYPASSL_TO_MIXOUTL 0 BYPASSR_TO_MIXOUTL Register 32h Analogue Left Mix 0 REGISTER BIT LABEL ADDRESS R51 (33h) 3 DACL_TO_MIXOUTR Analogue Right Mix 0 2 DACR_TO_MIXOUTR 1 ...

  • Page 136

    WM8903 REGISTER BIT LABEL ADDRESS R53 (35h) 3 DACL_MIXSPKL_VOL Analogue Spk Mix Left 1 2 DACR_MIXSPKL_VOL 1 BYPASSL_MIXSPKL_VOL 0 BYPASSR_MIXSPKL_VOL Register 35h Analogue Spk Mix Left 1 REGISTER BIT LABEL ADDRESS R54 (36h) 3 DACL_TO_MIXSPKR Analogue Spk Mix Right 0 ...

  • Page 137

    Pre-Production REGISTER BIT LABEL ADDRESS R57 (39h) 8 HPL_MUTE Analogue OUT1 Left 7 HPOUTVU 6 HPOUTLZC 5:0 HPOUTL_VOL[5:0] Register 39h Analogue OUT1 Left REGISTER BIT LABEL ADDRESS R58 (3Ah) 8 HPR_MUTE Analogue OUT1 Right 7 HPOUTVU 6 HPOUTRZC 5:0 HPOUTR_VOL[5:0] ...

  • Page 138

    WM8903 REGISTER BIT LABEL ADDRESS R59 (3Bh) 8 LINEOUTL_MUTE Analogue OUT2 Left 7 LINEOUTVU 6 LINEOUTLZC 5:0 LINEOUTL_VOL[5:0] Register 3Bh Analogue OUT2 Left REGISTER BIT LABEL ADDRESS R60 (3Ch) 8 LINEOUTR_MUTE Analogue OUT2 Right 7 LINEOUTVU 6 LINEOUTRZC 5:0 LINEOUTR_VOL[5:0] ...

  • Page 139

    Pre-Production REGISTER BIT LABEL ADDRESS R62 (3Eh) 8 SPKL_MUTE Analogue OUT3 Left 7 SPKVU 6 SPKLZC 5:0 SPKL_VOL[5:0] Register 3Eh Analogue OUT3 Left REGISTER BIT LABEL ADDRESS R63 (3Fh) 8 SPKR_MUTE Analogue OUT3 Right 7 SPKVU 6 SPKRZC 5:0 SPKR_VOL[5:0] ...

  • Page 140

    WM8903 REGISTER BIT LABEL ADDRESS R65 (41h) 1 SPK_DISCHARGE Analogue SPK Output Control 0 0 VROI Register 41h Analogue SPK Output Control 0 REGISTER BIT LABEL ADDRESS R67 (43h) 4 DCS_MASTER_ENA DC Servo 0 3:0 DCS_ENA[3:0] Register 43h DC Servo ...

  • Page 141

    Pre-Production REGISTER BIT LABEL ADDRESS R73 (49h) DCS_LOUTL_WRITE_VA 7:0 DC Servo 6 L [7:0] Register 49h DC Servo 6 REGISTER BIT LABEL ADDRESS R74 (4Ah) 7:0 DCS_LOUTR_WRITE_VA DC Servo 7 L [7:0] Register 4Ah DC Servo 7 REGISTER BIT LABEL ...

  • Page 142

    WM8903 REGISTER BIT LABEL ADDRESS R84 (54h) DCS_LOUTR_INTEG [7:0] 7:0 DC Servo Readback 4 Register 54h DC Servo Readback 4 REGISTER BIT LABEL ADDRESS R90 (5Ah) 7 HPL_RMV_SHORT Analogue HPL_ENA_OUTP 5 HPL_ENA_DLY 4 HPL_ENA 3 HPR_RMV_SHORT 2 ...

  • Page 143

    Pre-Production REGISTER BIT LABEL ADDRESS R98 (62h) 0 CP_ENA Charge Pump 0 Register 62h Charge Pump 0 REGISTER BIT LABEL ADDRESS R104 (68h) 0 CP_DYN_PWR Class W 0 Register 68h Class W 0 REGISTER BIT LABEL ADDRESS R108 (6Ch) 8 ...

  • Page 144

    WM8903 REGISTER BIT LABEL ADDRESS R110 (6Eh) 14 WSEQ_EOS Write Sequencer 2 11:8 WSEQ_DELAY[3:0] 7:0 WSEQ_DATA[7:0] Register 6Eh Write Sequencer 2 REGISTER BIT LABEL ADDRESS R111 (6Fh) 9 WSEQ_ABORT Write Sequencer 3 8 WSEQ_START 5:0 WSEQ_START_INDEX[5:0] Register 6Fh Write Sequencer ...

  • Page 145

    Pre-Production REGISTER BIT LABEL ADDRESS R116 (74h) 13:8 GP1_FN[5:0] GPIO Control 1 7 GP1_DIR 6 GP1_OP_CFG 5 GP1_IP_CFG 4 GP1_LVL 3 GP1_PD 2 GP1_PU 1 GP1_INTMODE 0 GP1_DB Register 74h GPIO Control 1 w DEFAULT DESCRIPTION GPIO 1 Pin Function ...

  • Page 146

    WM8903 REGISTER BIT LABEL ADDRESS R117 (75h) 13:8 GP2_FN[5:0] GPIO Control 2 7 GP2_DIR 6 GP2_OP_CFG 5 GP2_IP_CFG 4 GP2_LVL 3 GP2_PD 2 GP2_PU 1 GP2_INTMODE 0 GP2_DB Register 75h GPIO Control 2 w DEFAULT DESCRIPTION GPIO 2 Pin Function ...

  • Page 147

    Pre-Production REGISTER BIT LABEL ADDRESS R118 (76h) 13:8 GP3_FN[5:0] GPIO Control 3 7 GP3_DIR 6 GP3_OP_CFG 5 GP3_IP_CFG 4 GP3_LVL 3 GP3_PD 2 GP3_PU 1 GP3_INTMODE 0 GP3_DB Register 76h GPIO Control 3 w DEFAULT DESCRIPTION GPIO 3 Pin Function ...

  • Page 148

    WM8903 REGISTER BIT LABEL ADDRESS R119 (77h) 13:8 GP4_FN[5:0] GPIO Control 4 7 GP4_DIR 6 GP4_OP_CFG 5 GP4_IP_CFG 4 GP4_LVL 3 GP4_PD 2 GP4_PU 1 GP4_INTMODE 0 GP4_DB Register 77h GPIO Control 4 w DEFAULT DESCRIPTION GPIO 4 Pin Function ...

  • Page 149

    Pre-Production REGISTER BIT LABEL ADDRESS R120 (78h) 13:8 GP5_FN[5:0] GPIO Control 5 7 GP5_DIR 6 GP5_OP_CFG 5 GP5_IP_CFG 4 GP5_LVL 3 GP5_PD 2 GP5_PU 1 GP5_INTMODE 0 GP5_DB Register 78h GPIO Control 5 w DEFAULT DESCRIPTION GPIO 5 Pin Function ...

  • Page 150

    WM8903 REGISTER BIT LABEL ADDRESS R121 (79h) 15 MICSHRT_EINT Interrupt Status 1 14 MICDET_EINT 13 WSEQ_BUSY_EINT 4 GP5_EINT 3 GP4_EINT 2 GP3_EINT 1 GP2_EINT 0 GP1_EINT Register 79h Interrupt Status 1 w DEFAULT DESCRIPTION MICBIAS Short Circuit detect IRQ status ...

  • Page 151

    Pre-Production REGISTER BIT LABEL ADDRESS R122 (7Ah) 15 IM_MICSHRT_EINT Interrupt Status 1 Mask 14 IM_MICDET_EINT 13 IM_WSEQ_BUSY_EINT 4 IM_GP5_EINT 3 IM_GP4_EINT 2 IM_GP3_EINT 1 IM_GP2_EINT 0 IM_GP1_EINT Register 7Ah Interrupt Status 1 Mask REGISTER BIT LABEL ADDRESS R123 (7Bh) 15 ...

  • Page 152

    WM8903 REGISTER BIT LABEL ADDRESS R164 (A4h) 9 ADC_DIG_MIC Clock Rate Test 4 Register A4h Clock Rate Test 4 REGISTER BIT LABEL ADDRESS R172 (ACh) 6:4 PGA_BIAS [2:0] Analogue Output Bias 0 Register ACh Analogue Output Bias 0 REGISTER BIT ...

  • Page 153

    Pre-Production APPLICATIONS INFORMATION RECOMMENDED EXTERNAL COMPONENTS Design notes (1) Capacitor Type Decouplers: For C3, C4, C8, C9, a single 4.7uF X5R ceramic can be used. Charge pump capacitor types are critical. Capacitors must meet DC co-efficient requirement. See datasheet text. ...

  • Page 154

    WM8903 CAPACITOR REQUIRED CAPACITANCE CFB1-CFB2 1μF at 2vDC VPOS, VNEG 2μF at 2vDC (1) 2.2μF CPVDD (2) 4.7μF Table 77 Capacitor Examples The zobel network (C19,20,21,22, R9,10,11,12 in Figure 64) is required on HPOUTL/R and LINEOUTL/R if the output is ...

  • Page 155

    Pre-Production Figure 65 Mic Insert and Hook Switch Detect: Example MICBIAS Current Plot w WM8903 PP, Rev 3.1, August 2009 155 ...

  • Page 156

    WM8903 STEP 1 Mic not inserted. To detect mic insertion, Host processor must initialise interrupts and clear MICDET_INV = 0. At every step, the host processor should poll the interrupt status register. 2 Mechanical bounce of jack socket during Mic ...

  • Page 157

    Pre-Production PACKAGE DIMENSIONS FL: 40 PIN QFN PLASTIC PACKAGE D2 EXPOSED 6 GND PADDLE (A3 SEATING PLANE Dimensions (mm) Symbols MIN NOM A ...

  • Page 158

    ... WM8903 IMPORTANT NOTICE Wolfson Microelectronics plc (“Wolfson”) products and services are sold subject to Wolfson’s terms and conditions of sale, delivery and payment supplied at the time of order acknowledgement. Wolfson warrants performance of its products to the specifications in effect at the date of shipment. Wolfson reserves the right to make changes to its products and specifications or to discontinue any product or service without notice ...