WM8903LGEFK/RV Wolfson Microelectronics, WM8903LGEFK/RV Datasheet - Page 70

• Manufacturer Part Number: WM8903LGEFK/RV
• Description: Audio CODECs ULTRA LOW PWR HI FI CODEC
• Manufacturer: Wolfson Microelectronics

Specifications of WM8903LGEFK/RV

• Audio Codec Type: Stereo Codec
• No. Of Adcs: 2
• No. Of Dacs: 2
• No. Of Input Channels: 6
• No. Of Output Channels: 8
• Adc / Dac Resolution: 24bit
• Sampling Rate: 96kHz
• Operating Temperature Range: -40°C To +85°C
• Rohs Compliant: Yes
• Adcs / Dacs Signal To Noise Ratio: 96dB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

WM8903
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The register bits relating to pop suppression control are defined in Table 47.
R5 (05h)
VMID
Control 0
R65 (41h)
R90 (5Ah)
Analogue
HP 0
REGISTER
ADDRESS
BIT
7
6
0
1
0
7
6
5
4
3
2
1
0
VMID_TIE_ENA
BUFIO_ENA
VMID_BUF_ENA
SPK_DISCHARG
E
VROI
HPL_RMV_SHOR
T
HPL_ENA_OUTP
HPL_ENA_DLY
HPL_ENA
HPR_RMV_SHO
RT
HPR_ENA_OUTP
HPR_ENA_DLY
HPR_ENA
LABEL
DEFAULT
0
0
0
0
0
0
0
0
0
0
0
0
0
VMID buffer to Differential Lineouts
0 = Disabled
1 = Enabled
(only applies when relevant outputs
are disabled, ie. SPLK=0 or SPKR=0.
Resistance is controlled by VROI.)
VMID buffer to unused Inputs/Outputs
0 = Disabled
1 = Enabled
VMID Buffer Enable
0 = Disabled
1 = Enabled
Speaker Discharge Enable
0 = Disabled
1 = Enable
Select VMID_TIE_ENA resistance for
disabled Differential Lineouts
0 = 20k ohm
1 = 500 ohm
Removes HPL short
0 = HPL short enabled
1 = HPL short removed
In normal operation, this bit is set to 1
Enables HPL output stage
0 = Disabled
1 = Enabled
Enables HPL intermediate stage
0 = Disabled
1 = Enabled
Enables HPL input stage
0 = Disabled
1 = Enabled
Removes HPR short
0 = HPR short enabled
1 = HPR short removed
In normal operation, this bit is set to 1
Enables HPR output stage
0 = Disabled
1 = Enabled
Enables HPR intermediate stage
0 = Disabled
1 = Enabled
Enables HPR input stage
0 = Disabled
1 = Enabled
PP, Rev 3.1, August 2009
DESCRIPTION
Pre-Production
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