WM8903LGEFK/RV Wolfson Microelectronics, WM8903LGEFK/RV Datasheet - Page 35

• Manufacturer Part Number: WM8903LGEFK/RV
• Description: Audio CODECs ULTRA LOW PWR HI FI CODEC
• Manufacturer: Wolfson Microelectronics

Specifications of WM8903LGEFK/RV

• Audio Codec Type: Stereo Codec
• No. Of Adcs: 2
• No. Of Dacs: 2
• No. Of Input Channels: 6
• No. Of Output Channels: 8
• Adc / Dac Resolution: 24bit
• Sampling Rate: 96kHz
• Operating Temperature Range: -40°C To +85°C
• Rohs Compliant: Yes
• Adcs / Dacs Signal To Noise Ratio: 96dB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Pre-Production
DIGITAL MICROPHONE INTERFACE
Figure 28 Digital Microphone Interface Control
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MICROPHONE HOOK SWITCH CLOCKING REQUIREMENTS
A clock is required for the Hook Switch Detect circuit. This requires:
Any hook switch press (or release) which happens while one or more of the above criteria are not
satisfied (for example during a low power mode where the CPU has disabled MCLK) can still be
detected after the clocking conditions are met. The example sequence in Figure 26, where the event
happened while MCLK was stopped, is also applicable to microphone hook switch press (or release).
The WM8903 supports a two-channel digital microphone interface. The two-channel audio data is
multiplexed on the DMIC_DAT input and clocked by the DMIC_LR output.
The Digital Microphone Input, DMIC_DAT, is provided on the GPIO2/DMIC_DAT pin. The associated
clock, DMIC_LR, is provided on the GPIO1/DMIC_LR pin.
The Digital Microphone Input is selected as input by setting the ADC_DIG_MIC bit. When the Digital
Microphone Input is selected, the ADC input is deselected.
The Digital Microphone Interface configuration is illustrated in Figure 28.
Because the WM8903 digital microphone interface pins are powered in the DBVDD domain, it is
recommended to power the digital microphone from the same DBVDD supply as WM8903.
When GPIO1 is configured as DMIC_LR Clock output, the WM8903 outputs a clock which supports
Digital Mic operation at a multiple of the ADC sampling rate, in the range 1-3MHz. Note that,
although the ADC is not used when the digital microphone interface is selected, it is still necessary to
set the ADC sample rate in order to ensure correct operation of the DSP functions associated with
the digital microphone. See “Clocking and Sample Rates” for the details of the supported clocking
configurations.
When GPIO2/DMIC_DAT is configured as DMIC_DAT input, this pin is the digital microphone input.
Up to two microphones can share this pin; the two microphones are interleaved as illustrated in
Figure 29.
The digital microphone interface requires that MIC1 transmits a data bit each time that DMIC_LR is
high, and MIC2 transmits when DMIC_LR is low. The WM8903 samples the digital microphone data
in the middle of each DMIC_LR clock phase. Each microphone must tri-state its data output when
the other microphone is transmitting.
1.
2.
3.
MCLK to be present
CLK_SYS_ENA = 1
WSMD_CLK_ENA = 1
PP, Rev 3.1, August 2009
WM8903
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