CS42518-CQZR Cirrus Logic Inc, CS42518-CQZR Datasheet - Page 21

• Manufacturer Part Number: CS42518-CQZR
• Description: Audio CODECs IC 110dB 192kHz 8Ch Mlt-Ch CODEC
• Manufacturer: Cirrus Logic Inc

Specifications of CS42518-CQZR

• Number Of Adc Inputs: 2
• Number Of Dac Outputs: 8
• Conversion Rate: 192 KSPs
• Interface Type: Serial (I2C, SPI)
• Resolution: 24 bit
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: LQFP-64
• Minimum Operating Temperature: - 10 C
• Number Of Channels: 2 ADC, 8 DAC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DS584F1
4. APPLICATIONS
4.1
4.2
4.2.1
Overview
The CS42518 is a highly integrated mixed-signal 24-bit audio codec comprised of 2 analog-to-digital con-
verters (ADC), implemented using multi-bit delta-sigma techniques, 8 digital-to-analog converters (DAC)
and a 192 kHz digital audio S/PDIF receiver. Other functions integrated within the codec include indepen-
dent digital volume controls for each DAC, digital de-emphasis filters for DAC and S/PDIF, digital gain con-
trol for ADC channels, ADC high-pass filters, an on-chip voltage reference, and an 8:2 mux for S/PDIF
sources. All serial data is transmitted through two configurable serial audio interfaces with standard serial
interface support as well as enhanced one-line modes of operation, allowing up to 6 channels of serial audio
data on one data line. All functions are configured through a serial control port operable in SPI mode or in
I²C mode. Figure
The CS42518 operates in one of three oversampling modes based on the input sample rate. Mode selection
is determined by the FM bits in register
(SSM) supports input sample rates up to 50 kHz and uses a 128x oversampling ratio. Double-Speed Mode
(DSM) supports input sample rates up to 100 kHz and uses an oversampling ratio of 64x. Quad-Speed
Mode (QSM) supports input sample rates up to 192 kHz and uses an oversampling ratio of 32x.
Using the receiver clock recovery PLL, a low-jitter clock is recovered from the incoming S/PDIF data stream.
The recovered clock or an externally supplied clock attached to the OMCK pin can be used as the System
Clock.
Analog Inputs
Line-Level Inputs
AINR+, AINR-, AINL+, and AINL- are the line-level differential analog inputs. The analog signal must be
externally biased to VQ, approximately 2.7 V, before being applied to these inputs. The level of the signal
can be adjusted for the left and right ADC independently through the ADC Left and Right Channel Gain
Control Registers on
above positive full scale or below negative full scale, the ADC will output 7FFFFFH or 800000H, respec-
tively and cause the ADC Overflow bit in the register
page 63
has occurred in the ADC. See
for proper configuration. Figure
page 73
for a recommended input buffer.
to be set to a ‘1’. The RXP/GPO pins may also be configured to indicate an overflow condition
5
shows the recommended connections for the CS42518.
4.1 V
2.7 V
1.3 V
4.1 V
2.7 V
1.3 V
Full-Scale Input Level= (AIN+) - (AIN-)= 5.6 Vpp
page
61. The ADC output data is in two’s complement binary format. For inputs
Figure 6. Full-Scale Analog Input
“RXP/General-Purpose Pin Control (addresses 29h to 2Fh)” on page 69
6
shows the full-scale analog input levels. See
“Functional Mode (address 03h)” on page
“Interrupt Status (address 20h) (Read Only)” on
AIN+
AIN-
48. Single-Speed Mode
“ADC Input Filter” on
CS42518
21