CS42518-CQZR Cirrus Logic Inc, CS42518-CQZR Datasheet - Page 33

Audio CODECs IC 110dB 192kHz 8Ch Mlt-Ch CODEC

CS42518-CQZR

Manufacturer Part Number
CS42518-CQZR
Description
Audio CODECs IC 110dB 192kHz 8Ch Mlt-Ch CODEC
Manufacturer
Cirrus Logic Inc
Datasheet

Specifications of CS42518-CQZR

Number Of Adc Inputs
2
Number Of Dac Outputs
8
Conversion Rate
192 KSPs
Interface Type
Serial (I2C, SPI)
Resolution
24 bit
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Package / Case
LQFP-64
Minimum Operating Temperature
- 10 C
Number Of Channels
2 ADC, 8 DAC
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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DS584F1
4.6.4
Functional Mode Register (addr = 03h)
Interface Format Register (addr = 04h)
Misc. Control Register (addr = 05h)
Set CODEC_FMx = SAI_FMx = 00,01,10
Set ADC_SP SELx = 00
Set DIFx bits to proper serial format
Set ADC_OLx bits = 00,01,10
Set DAC_OLx bits = 00,01,10
Set CODEC_SP M/S = 1
Set SAI_SP M/S = 1
Set EXT ADC SCLK = 0
ADC Mode
4.6.4.1
One-Line Mode Configuration #1 can support up to 8 channels of DAC data, 6 channels of ADC data and
2 channels of S/PDIF received data. This is the only configuration which will support up to 24-bit samples
at a sampling frequency of 48 kHz on all channels for both the DAC and ADC.
Register / Bit Settings
One-Line Mode (OLM) Configurations
Line Mode
Not One-
One-Line
One-Line
Mode #1
Mode #2
OLM Config #1
CS5361
CS5361
SDOUT1
SDOUT2
CX_SCLK=64 Fs
CX_LRCK=SSM/DSM/QSM
SAI_SCLK=64 Fs
SAI_LRCK=CX_LRCK
CX_SCLK=128 Fs
CX_LRCK=SSM/DSM
SAI_SCLK=64 Fs
SAI_LRCK=CX_LRCK
CX_SCLK=256 Fs
CX_LRCK=SSM
SAI_SCLK=64 Fs
SAI_LRCK=CX_LRCK
SCLK
MCLK
LRCK
Not One-Line Mode
Figure 16. OLM Configuration #1
RMCK
ADCIN1
ADCIN2
CS42518
CX_LRCK must equal SAI_LRCK; sample rate conversion not supported
Select ADC operating mode, see table below for valid combinations
Select DAC operating mode, see table below for valid combinations
Configure ADC data on CX_SDOUT, S/PDIF data on SAI_SDOUT
SAI_SDOUT
CX_SDOUT
SAI_LRCK
SAI_SCLK
CX_SDIN1
CX_SDIN2
CX_SDIN3
CX_SDIN4
Select the digital interface format when not in One-Line Mode
CX_SCLK
CX_LRCK
Configure Serial Audio Interface Port to master mode.
Identify external ADC clock source as SAI Serial Port.
CX_SCLK=128 Fs
CX_LRCK=SSM/DSM
SAI_SCLK=64 Fs
SAI_LRCK=CX_LRCK
CX_SCLK=128 Fs
CX_LRCK=SSM/DSM
SAI_SCLK=64 Fs
SAI_LRCK=CX_LRCK
Configure CODEC Serial Port to master mode.
SPDIF Data
64Fs,128Fs, 256Fs
ADC Data
One-Line Mode #1
DAC Mode
64Fs
not valid
SDIN_PORT1
MCLK
SCLK_PORT1
LRCK_PORT1
SCLK_PORT2
LRCK_PORT2
SDIN_PORT2
SCLK_PORT3
LRCK_PORT3
SDOUT1_PORT3
SDOUT2_PORT3
SDOUT3_PORT3
SDOUT4_PORT3
Description
DIGITAL AUDIO
PROCESSOR
CX_SCLK=256 Fs
CX_LRCK=SSM
SAI_SCLK=64 Fs
SAI_LRCK=CX_LRCK
One-Line Mode #2
not valid
not valid
CS42518
33

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