CS42518-CQZR Cirrus Logic Inc, CS42518-CQZR Datasheet - Page 75

• Manufacturer Part Number: CS42518-CQZR
• Description: Audio CODECs IC 110dB 192kHz 8Ch Mlt-Ch CODEC
• Manufacturer: Cirrus Logic Inc

Specifications of CS42518-CQZR

• Number Of Adc Inputs: 2
• Number Of Dac Outputs: 8
• Conversion Rate: 192 KSPs
• Interface Type: Serial (I2C, SPI)
• Resolution: 24 bit
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: LQFP-64
• Minimum Operating Temperature: - 10 C
• Number Of Channels: 2 ADC, 8 DAC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DS584F1
9.2.1
9.2.1.1
In many applications, the channel status blocks for the A and B channels will be identical. In this situation,
the user may read a byte from one of the channel's blocks since the corresponding byte for the other chan-
nel will likely be the same. One-Byte Mode takes advantage of the often identical nature of A and B channel
status data. When reading data in One-Byte Mode, a single byte is returned, which can be from channel A
or B data, depending on a register control bit.
One-Byte Mode saves the user substantial control port access time, as it effectively accesses two bytes
worth of information in 1 byte's worth of access time. If the control port's auto-increment addressing is used
in combination with this mode, multi-byte accesses, such as full-block reads, can be done especially effi-
ciently.
9.2.1.2
There are those applications in which the A and B channel status blocks will not be the same, and the user
is interested in accessing both blocks. In these situations, Two-Byte Mode should be used to access the
E buffer.
In this mode, a read will cause the CS42518 to output two bytes from its control port. The first byte out will
represent the A channel status data, and the second byte will represent the B channel status data.
Channel Status Data E Buffer Access
The user can monitor the incoming Channel Status data by reading the E buffer, which is mapped into the
register space of the CS42518 through the control port Data Buffer. The Data Buffer must first be config-
ured to point to the address space of the C data. This is accomplished by setting the BSEL bit to ‘0’ in the
register
The user can configure the Interrupt Mask Register to cause an interrupt whenever any data-bit changes
are detected when D to E Channel Status buffer transfers occur. If no data bits have changed within the
current transfer of data from D to E, no interrupt will be generated. This allows determination of the ac-
ceptable time periods to interact with the E buffer. See
details.
The E buffer is organized as 24 x 16-bit words. For each word the MS Byte is the A channel data, and the
LS Byte is the B channel data (see
as One-Byte Mode and Two-Byte Mode. The desired mode is selected by setting the CAM bit in the Chan-
nel Status Data Buffer Control Register.
“Channel Status Data Buffer Control (address 24h)” on page
One-Byte Mode
Two-Byte Mode
Figure 26. Channel Status Data Buffer Structure
Receiver
S/PDIF
From
Figure
Received
Data
Buffer
26). There are two methods of accessing this memory, known
D
“Interrupt Mask (address 21h)” on page 64
8-bits
A
Control Port
words
E
8-bits
24
B
65.
CS42518
for more
75