CS42518-CQZR Cirrus Logic Inc, CS42518-CQZR Datasheet - Page 37

• Manufacturer Part Number: CS42518-CQZR
• Description: Audio CODECs IC 110dB 192kHz 8Ch Mlt-Ch CODEC
• Manufacturer: Cirrus Logic Inc

Specifications of CS42518-CQZR

• Number Of Adc Inputs: 2
• Number Of Dac Outputs: 8
• Conversion Rate: 192 KSPs
• Interface Type: Serial (I2C, SPI)
• Resolution: 24 bit
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: LQFP-64
• Minimum Operating Temperature: - 10 C
• Number Of Channels: 2 ADC, 8 DAC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DS584F1
Functional Mode Register (addr = 03h)
Interface Format Register (addr = 04h)
Misc. Control Register (addr = 05h)
ADC Mode
CX_SDOUT= ADC Data
Set CODEC_FMx = 00,01,10
Set SAI_FMx = 00,01,10
Set ADC_SP SELx = 00,01,10
Set DIFx bits to proper serial format
Set ADC_OLx bits = 00
Set DAC_OLx bits = 00,01
Set CODEC_SP M/S = 0 or 1
Set SAI_SP M/S = 0 or 1
Set EXT ADC SCLK = 0
SAI_SDOUT=ADC or
S/PDIF Data
4.6.4.5
This One-Line Mode configuration can support up to 8 channels of DAC data 2 channels of ADC data and
2 channels of S/PDIF received data and will handle up to 24-bit samples at a sampling frequency of 48 kHz
on all channels for both the DAC and ADC. The output data stream of the internal ADCs can be configured
to use the CX_SDOUT output and run at the CODEC_SP clock speeds or to use the SAI_SDOUT data
output and run at the SAI_SP rate. The CODEC_SP and SAI_SP can operate at different Fs rates.
Register / Bit Settings
Line Mode
One-Line
One-Line
Not One-
Mode #1
Mode #2
OLM Config #5
CX_SCLK=64 Fs
CX_LRCK=SSM/DSM/QSM
SAI_SCLK=64 Fs
SAI_LRCK=SSM/DSM/QSM
Not One-Line Mode
not valid
not valid
RMCK
ADCIN1
ADCIN2
Figure 20. OLM Configuration #5
CS42518
SAI_SDOUT
CX_SDOUT
SAI_SCLK
SAI_LRCK
CX_SDIN1
CX_SDIN2
CX_SDIN3
CX_SDIN4
CX_LRCK
CX_SCLK
Set ADC operating mode to Not One Line Mode since only 2 channels of
CX_LRCK can run at SSM, DSM, or QSM independent of SAI_LRCK
SAI_LRCK can run at SSM, DSM, or QSM independent of CX_LRCK
CX_SCLK=128 Fs
CX_LRCK=SSM/DSM
SAI_SCLK=64 Fs
SAI_LRCK=SSM/DSM/QSM
Configure ADC data to use CX_SDOUT and CODEC_SP clocks, or
Select DAC operating mode, see table below for valid combinations
64Fs,128Fs, 256Fs
64Fs,128Fs, 256Fs
ADC Data
SPDIF or ADC Data
Set Serial Audio Interface Port to master mode or slave mode.
Select the digital interface format when not in one line mode
One-Line Mode #1
Set CODEC Serial Port to master mode or slave mode.
External ADCs are not used. Leave bit in default state.
DAC Mode
not valid
not valid
SCLK_PORT1
LRCK_PORT1
SDIN_PORT1
SCLK_PORT2
SDIN_PORT2
LRCK_PORT3
SDOUT1_PORT3
SDOUT2_PORT3
SDOUT3_PORT3
SDOUT4_PORT3
MCLK
LRCK_PORT2
SCLK_PORT3
DIGITAL AUDIO
PROCESSOR
SAI_SDOUT and SAI_SP cocks.
ADC are supported
Description
One-Line Mode #2
not valid
not valid
not valid
CS42518
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