CS42518-CQZR Cirrus Logic Inc, CS42518-CQZR Datasheet - Page 26

• Manufacturer Part Number: CS42518-CQZR
• Description: Audio CODECs IC 110dB 192kHz 8Ch Mlt-Ch CODEC
• Manufacturer: Cirrus Logic Inc

Specifications of CS42518-CQZR

• Number Of Adc Inputs: 2
• Number Of Dac Outputs: 8
• Conversion Rate: 192 KSPs
• Interface Type: Serial (I2C, SPI)
• Resolution: 24 bit
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: LQFP-64
• Minimum Operating Temperature: - 10 C
• Number Of Channels: 2 ADC, 8 DAC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

26
4.5.2
4.5.3
4.5.4
OMCK System Clock Mode
A special clock-switching mode is available that allows the clock that is input through the OMCK pin to be
used as the internal master clock. This feature is controlled by the SW_CTRLx bits in register
trol (address 06h)” on page
ter clock functionality. The clock auto-switching mode allows the clock input through OMCK to be used as
a clock in the system without any disruption when the PLL loses lock, for example, when the input is re-
moved from the receiver. This clock-switching is done glitch-free. A clock adhering to the specifications
detailed in the Switching Characteristics table on
that the FRC_PLL_LK bit is set to ‘0’ (See
Master Mode
In Master Mode, the serial interface timings are derived from an external clock attached to OMCK or from
the output of the PLL with an input reference to either the S/PDIF Receiver recovered clock or the
SAI_LRCK input from the Serial Audio Interface Port. Master clock selection and operation is configured
with the SW_CTRL1:0 bits in the Clock Control Register (See
page
Slave Mode
In Slave Mode, CX_LRCK, CX_SCLK and/or SAI_LRCK, SAI_SCLK operate as inputs. The Left/Right
clock signal must be equal to the sample rate, Fs, and must be synchronously derived from the supplied
master clock, OMCK, or the output of the PLL. The serial bit clock, CX_SCLK and/or SAI_SCLK, must be
synchronously derived from the master clock and be equal to 128x, 64x, 48x or 32x Fs, depending on the
interface format selected and desired speed mode.
When the device is clocked from OMCK, the frequency of OMCK must be at least twice the frequency of
the fastest Slave Mode, SCLK. For example, if both serial ports are in Slave Mode with one SCLK running
at 32x Fs and the other at 64x Fs, the slowest OMCK signal that can be used to clock the device is
128x Fs.
Sample
(kHz)
Rate
192
53).The supported PLL output frequencies are shown in Table
48
96
12.2880 18.4320 24.5760
256x
Sample
(kHz)
-
-
Rate
176.4
44.1
88.2
192
32
48
64
96
Single-Speed
(4 to 50 kHz)
384x
Table 2. Common PLL Output Clock Frequencies
-
-
Single Speed
Table 1. Common OMCK Clock Frequencies
(4 to 50 kHz)
53. An advanced auto-switching mode is also implemented to maintain mas-
11.2896
12.2880
8.1920
256x
512x
-
-
-
-
-
-
-
12.2880 18.4320 24.5760
128x
-
-
“Force PLL Lock (FRC_PLL_LK)” on page
PLL Output (MHz)
(50 to 100 kHz)
Double-Speed
(50 to 100 kHz)
OMCK (MHz)
Double Speed
16.3840
22.5792
24.5760
192x
page 12
256x
-
-
-
-
-
-
-
256x
must be applied to the OMCK pin at all times
-
-
(100 to 192 kHz)
Quad Speed
12.2880 18.4320 24.5760
64x
2
45.1584
49.1520
“Clock Control (address 06h)” on
-
-
256x
(100 to 192 kHz)
below.
Quad-Speed
-
-
-
-
-
-
96x
-
-
128x
54).
-
-
CS42518
“Clock Con-
DS584F1