PSB21384HV1.3 Infineon Technologies, PSB21384HV1.3 Datasheet - Page 116

• Manufacturer Part Number: PSB21384HV1.3
• Description: Telecom ICs AMuLaw/Speech CODEC w/ ST Transceiver
• Manufacturer: Infineon Technologies

Specifications of PSB21384HV1.3

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Data Sheet
The HDLC controller indicates to the host that a new data block can be read from the
RFIFO by means of an RPF interrupt (see previous chapter). User data is stored in the
RFIFO and information about the received frame is available in the RSTA, RBCL and
RBCH registers which are listed in table 11.
Table 11
Receive Information at RME Interrupt
Information
Type of frame
(Command/
Response)
Recognition of SAPI
Recognition of TEI
Result of CRC check
(correct/incorrect)
Valid Frame
Abort condition detected
(yes/no)
Data overflow during reception
of a frame (yes/no)
Number of bytes received in
RFIFO
Message length
RFIFO Overflow
Location
RFIFO
(last byte)
RFIFO
(last byte)
RFIFO
(last byte)
RFIFO
(last byte)
RFIFO
(last byte)
RFIFO
(last byte)
RFIFO
(last byte)
RBCL Reg. RBC4-0
RBCH Reg.
RBCL Reg.
RBCH Reg. OV
106
Bit
C/R
SA1, 0
TA
CRC
VFR
RAB
RDO
RBC11-0 All
Mode
Non-auto mode,
2-byte address field
Transparent mode 1
Non-auto mode,
2-byte address field
Transparent mode 1
All except
transparent mode 0
All
All
All
All
All
All
HDLC Controller
PSB 21381/2
PSB 21383/4
2001-03-12