PSB21384HV1.3 Infineon Technologies, PSB21384HV1.3 Datasheet - Page 74

• Manufacturer Part Number: PSB21384HV1.3
• Description: Telecom ICs AMuLaw/Speech CODEC w/ ST Transceiver
• Manufacturer: Infineon Technologies

Specifications of PSB21384HV1.3

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Data Sheet
The availability of the line interface D channel is indicated in bit 5 "Stop/Go" (S/G) of the
DD last octet of channel 2 (figure 40).
S/G = 1 : stop
S/G = 0 : go
Figure 40
Structure of Last Octet of Ch2 on DD
The Stop/Go bit is available to other layer-2 devices connected to the IOM to determine
if they can access the D channel of the S/T interface.
For test purposes the E bits received on the S/T interface are transparently transferred
data downstream to bits 7 and 6 of the last octet of channel 2.
2.2.7.2 S-Bus Priority Mechanism for D-Channel
The S-bus D-channel access procedure specified in ITU I.430 was defined to organize
D-channel access with multiple TEs connected to a single S-bus (see figure 41).
The D-channel S-bus status is indicated towards the IOM-2 interface with the S/G bit
(see previous section).
The priority mechanism as specified in ITU I.430 is fully implemented in the SCOUT. For
this purpose the D-channel collision detection according to ITU I.430 must be enabled
by setting DIM2-0 in the register MODEH to ’0x1’.
In this case the SCOUT continuously compares the D data bits with the received E-echo
bits. If the S/G bit is set to ’0’ the 1st D-bit, contained in the IOM-2 frame following the S/
G bit appears on the S/T bus in time (after 8, 9, 10, 11 consecutive logical ’1’s).
The priority class (priority 8 or priority 10) is selected by transferring the appropriate
activation command via the Command/Indication (C/I) channel of the IOM-2 interface to
the SCOUT S-interface. If the activation is initiated by a TE, the priority class is selected
implicitly by the choice of the activation command. If the S-interface is activated from the
NT, an activation command selecting the desired priority class should be programmed
at the TE on reception of the activation indication (AI8 or AI10).
DD
MR
MX
64
Available/Blocked
Stop/Go
E bits received on S
MR
MX
A/B
S/G
PSB 21381/2
PSB 21383/4
tic_octetdd-s0.vsd
Interfaces
2001-03-12