PSB21384HV1.3 Infineon Technologies, PSB21384HV1.3 Datasheet - Page 215

• Manufacturer Part Number: PSB21384HV1.3
• Description: Telecom ICs AMuLaw/Speech CODEC w/ ST Transceiver
• Manufacturer: Infineon Technologies

Specifications of PSB21384HV1.3

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

7.2.11
Value after reset: 7F
MASK
For the MASK register following logical states are applied:
0: Interrupt is not masked
1: Interrupt is masked
Each interrupt source in the ISTA register can be selectively masked by setting to ’1’ the
corresponding bit in MASK. Masked interrupt status bits are not indicated when ISTA is
read. Instead, they remain internally stored and pending, until the mask bit is reset to ’0’.
Note: In the event of a C/I channel change, CIC is set in ISTA even if the corresponding
7.2.12
Value after reset: 00
MODE1
MCLK
The Master Clock Frequency bits control the microcontroller clock output corresponding
to the following table.
Bit 7 Bit 6 MCLK frequency
Data Sheet
0
0
1
1
mask bit in MASK is active, but no interrupt is generated.
0
1
0
1
MASK - Mask Register
MODE1 - Mode1 Register
7
7
MODE1.CDS = ’0’
0
MCLK
... Master Clock Frequency
3.84 MHz
0.96 MHz
7.68 MHz
disabled
with
H
H
ST
CIC
0
WTC1 WTC2
TIN
205
WOV TRAN MOS HDLC
CFS
Detailed Register Description
RSS2 RSS1 RD/WR (3D
0
0
PSB 21381/2
PSB 21383/4
2001-03-12
WR (3C
H
H
)
)