PSB21384HV1.3 Infineon Technologies, PSB21384HV1.3 Datasheet - Page 73

• Manufacturer Part Number: PSB21384HV1.3
• Description: Telecom ICs AMuLaw/Speech CODEC w/ ST Transceiver
• Manufacturer: Infineon Technologies

Specifications of PSB21384HV1.3

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The arbitration mechanism is implemented in the last octet in IOM channel 2 of the IOM-
2 interface (see figure 39). An access request to the TIC bus may either be generated
by software ( P access to the C/I channel) or by the SCOUT itself (transmission of an
HDLC frame in the D-channel). A software access request to the bus is effected by
setting the BAC bit (CIX0 register) to ’1’.
In the case of an access request, the SCOUT checks the Bus Accessed-bit BAC (bit 5
of DU last octet of channel 2, see figure 39) for the status "bus free“, which is indicated
by a logical ’1’. If the bus is free, the SCOUT transmits its individual TIC bus address TAD
programmed in the CIX0 register and compares it bit by bit with the value on DU. If a sent
bit set to ’1’ is read back as ’0’ because of the access of another D-channel source with
a lower TAD, the SCOUT withdraws immediately from the TIC bus. The TIC bus is
occupied by the device which sends its address error-free. If more than one device
attempt to seize the bus simultaneously, the one with the lowest address wins and starts
D-channel transmission.
Figure 39
Structure of Last Octet of Ch2 on DU
When the TIC bus is seized by the SCOUT, the bus is identified to other devices as
occupied via the DU channel 2 Bus Accessed-bit state ’0’ until the access request is
withdrawn. After a successful bus access, the SCOUT is automatically set into a lower
priority class, that is, a new bus access cannot be performed until the status "bus free"
is indicated in two successive frames.
If none of the devices connected to the IOM interface requests access to the D and C/I
channels, the TIC bus address 7 will be present. The device with this address will
therefore have access, by default, to the D and C/I channels.
Note: Bit BAC (CIX0 register) should be reset by the µP when access to the C/I channels
Data Sheet
DU
is no more requested, to grant other devices access to the D and C/I channels.
MR
MX
63
TIC-Bus Address (TAD 2-0)
Bus Accessed (’1’ no TIC-Bus Access)
MR
MX
TAD
BAC
PSB 21381/2
PSB 21383/4
tic_octet-du.vsd
Interfaces
2001-03-12