PSB21384HV1.3 Infineon Technologies, PSB21384HV1.3 Datasheet - Page 246

• Manufacturer Part Number: PSB21384HV1.3
• Description: Telecom ICs AMuLaw/Speech CODEC w/ ST Transceiver
• Manufacturer: Infineon Technologies

Specifications of PSB21384HV1.3

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Data Sheet
7.4.13
The programming of the CRAM Control Register (CCR) and the CRAM Status Register
(CSR) is intended for a back-up procedure for the direct access to individual CRAM
coefficients. A detailed description can be found in chapter 4.8.2.1.
CRAM Status Register (CSR)
Value after reset: 00
CCR
DCA
Read-back of the programmed value
BSYB
0: Momentary there is no transfer of CRAM data to the temporary area running. CRAM
1: Transfer of the CRAM block <CBADR> is running. CRAM access via microcontroller
CBADR
Read-back of the programmed value
CRAM Control Register (CCR)
Value after reset: 00
CCR
DCA
0: The normal CRAM area (80
1: The temporary CRAM area (coefficient block with 8 bytes corresponding to the
SBP
0: No back-up is initiated
1: A transition to SBP = ’1’ starts the back-up of the CRAM block <CBADR> into the
access via microcontroller interface is possible
interface is not allowed
COP_x sequences) is accessed by the codec DSP. The switching to the temporary
CRAM block happens as soon as the transfer of the block has completed (BSYB = ’0’)
temporary CRAM area
7
7
CRAM Control (CCR) and Status (CSR) Register
0
0
... DSP CRAM Access
... Busy Back-up Procedure
... CRAM Block Address
... DSP CRAM Access
... Start Back-up Procedure
H
H
0
0
DCA BSYB
DCA
H
to FF
SBP
H
) is accessed by the codec DSP
236
CBADR
CBADR
Detailed Register Description
0
0
PSB 21381/2
PSB 21383/4
2001-03-12
WR (6F
RD (6F
H
H
)
)