PSB21384HV1.3 Infineon Technologies, PSB21384HV1.3 Datasheet - Page 201

• Manufacturer Part Number: PSB21384HV1.3
• Description: Telecom ICs AMuLaw/Speech CODEC w/ ST Transceiver
• Manufacturer: Infineon Technologies

Specifications of PSB21384HV1.3

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

7.1.15
Value after reset: 0E
RSTA
VFR
Determines whether a valid frame has been received.
The frame is valid (1) or invalid (0).
A frame is invalid when there is not a multiple of 8 bits between flag and frame end (flag,
abort).
RDO
If RDO=1, at least one byte of the frame has been lost, because it could not be stored in
RFIFO.
CRC
The CRC is correct (1) or incorrect (0).
RAB
The receive message was aborted by the remote station (1), i.e. a sequence of seven
1’s was detected before a closing flag.
SA1-0
TA
SA1-0 are significant in non-auto-mode with a two-byte address field, as well as in
transparent mode 3. TA is significant in all modes except in transparent modes 0 and 1.
Two programmable SAPI values (SAP1, SAP2) plus a fixed group SAPI (SAPG of value
FC/FE
of value FF
The result of the address comparison is given by SA1-0 and TA, as follows:
C/R
The C/R bit contains the C/R bit of the received frame (Bit1 in the SAPI address)
Note: The contents of RSTA corresponds to the last received HDLC frame; it is
Note: If SAP1 and SAP2 contains identical values, the combination 001 will be omitted.
Data Sheet
duplicated into RFIFO for every frame (last byte of frame)
H
), and two programmable TEI values (TEI1, TEI2) plus a fixed group TEI (TEIG
RSTA - Receive Status Register
H
7
VFR
), are available for address comparison.
... Valid Frame
... Receive Data Overflow
... CRC Check
... Receive Message Aborted
... SAPI Address Identification
... TEI Address Identification
... Command/Response
RDO
H
CRC
RAB
191
SA1
SA0
Detailed Register Description
C/R
0
TA
PSB 21381/2
PSB 21383/4
2001-03-12
RD (28
H
)