PSB21384HV1.3 Infineon Technologies, PSB21384HV1.3 Datasheet - Page 85

• Manufacturer Part Number: PSB21384HV1.3
• Description: Telecom ICs AMuLaw/Speech CODEC w/ ST Transceiver
• Manufacturer: Infineon Technologies

Specifications of PSB21384HV1.3

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

After multi-frame synchronization has been established, the Q data will be inserted at the
upstream (TE
When synchronization is not achieved or lost, each received F
transmitted F
Multi-frame synchronization is achieved after two complete multi-frames have been
detected with reference to F
if bit errors in F
frames. The synchronization state is indicated by the MSYN bit in the S/Q-channel
receive register (SQRR).
The multi-frame synchronization can be enabled or disabled by programming the MFEN
bit in the S/Q-channel transmit register (SQXR).
2.3.3.1
To trigger the microcontroller for a multi-frame access an interrupt can be generated
once per multi-frame or if the 4 bits of the received S-channel have changed (see
chapter 7.2.8).
In both cases the microcontroller has access to the multi-frame within 18 S frames (4.5
ms).
2.3.4
The following figure illustrates the line code. A binary ONE is represented by no line
signal. Binary ZEROs are coded with alternating positive and negative pulses with two
exceptions:
The first binary ZERO following the framing balance bit is of the same polarity as the
framing-balancing bit and the last binary ZERO before the framing bit is of the same
polarity as the framing bit (required code violations).
Figure 46
S/T -Interface Line Code (without code violation)
Data Sheet
Interrupt Handling for Multi-Framing
Line Code
A
bit.
A
/N bit or M bit positions have been detected in two consecutive multi-
NT) F
A
bit position in each 5th S/T frame (see table 9).
A
/N bit and M bit positions. Multi-frame synchronization is lost
75
A
bit is mirrored to the next
PSB 21381/2
PSB 21383/4
Interfaces
2001-03-12