PSMN2R0-30YL,115 NXP Semiconductors, PSMN2R0-30YL,115 Datasheet - Page 3

• Manufacturer Part Number: PSMN2R0-30YL,115
• Description: MOSFET N-CH 30V 100A LFPAK
• Manufacturer: NXP Semiconductors
• Series: TrenchMOS™r

Specifications of PSMN2R0-30YL,115

• Package / Case: LFPak-4
• Fet Type: MOSFET N-Channel, Metal Oxide
• Fet Feature: Logic Level Gate
• Rds On (max) @ Id, Vgs: 2 mOhm @ 15A, 10V
• Drain To Source Voltage (vdss): 30V
• Current - Continuous Drain (id) @ 25° C: 100A
• Vgs(th) (max) @ Id: 2.15V @ 1mA
• Gate Charge (qg) @ Vgs: 64nC @ 10V
• Input Capacitance (ciss) @ Vds: 3980pF @ 12V
• Power - Max: 97W
• Mounting Type: Surface Mount
• Minimum Operating Temperature: - 55 C
• Configuration: Single
• Transistor Polarity: N-Channel
• Resistance Drain-source Rds (on): 2 mOhms
• Drain-source Breakdown Voltage: 30 V
• Gate-source Breakdown Voltage: 20 V
• Continuous Drain Current: 100 A
• Power Dissipation: 97 W
• Maximum Operating Temperature: + 175 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 568-4679-2; 934063069115; PSMN2R0-30YL T/R

NXP Semiconductors
4. Limiting values
Table 4.
In accordance with the Absolute Maximum Rating System (IEC 60134).
[1]
PSMN2R0-30YL
Product data sheet
Symbol
V
V
V
V
I
I
P
T
T
Source-drain diode
I
I
Avalanche ruggedness
E
D
DM
S
SM
Fig 1.
stg
j
DS
DSM
DGR
GS
tot
DS(AL)S
(A)
Continuous current is limited by package.
I
D
120
100
80
60
40
20
0
mounting base temperature
Continuous drain current as a function of
0
Limiting values
Parameter
drain-source voltage
peak drain-source voltage
drain-gate voltage
gate-source voltage
drain current
peak drain current
total power dissipation
storage temperature
junction temperature
source current
peak source current
non-repetitive drain-source
avalanche energy
50
(1)
100
150
All information provided in this document is subject to legal disclaimers.
T
003aac471
mb
(°C)
200
Conditions
T
t
E
T
V
V
see
pulsed; t
see
T
T
pulsed; t
V
V
p
Rev. 4 — 10 March 2011
j
j
mb
mb
DS(AL)
GS
GS
GS
sup
≤ 25 ns; f ≤ 500 kHz;
≥ 25 °C; T
≥ 25 °C; T
Figure 3
Figure 3
= 25 °C; see
= 25 °C
= 10 V; T
= 10 V; T
= 10 V; T
≤ 30 V; R
≤ 280 nJ; pulsed
p
p
≤ 10 µs; T
≤ 10 µs; T
j
j
N-channel 30 V 2 mΩ logic level MOSFET in LFPAK
Fig 2.
≤ 175 °C
≤ 175 °C; R
mb
mb
j(init)
GS
= 100 °C; see
= 25 °C; see
= 50 Ω; unclamped
P
Figure 2
(%)
= 25 °C; I
der
120
80
40
mb
mb
0
function of mounting base temperature
Normalized total power dissipation as a
0
= 25 °C;
= 25 °C
GS
D
= 20 kΩ
= 100 A;
Figure
Figure 1
50
PSMN2R0-30YL
1;
100
[1]
[1]
[1]
Min
-
-
-
-20
-
-
-
-
-55
-55
-
-
-
150
© NXP B.V. 2011. All rights reserved.
T
mb
175
175
Max
30
35
30
20
100
100
667
97
100
667
151
03aa16
(°C)
200
Unit
V
V
V
V
A
A
A
W
°C
°C
A
A
mJ
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