PSMN2R0-30YL,115 NXP Semiconductors, PSMN2R0-30YL,115 Datasheet - Page 8

MOSFET N-CH 30V 100A LFPAK

PSMN2R0-30YL,115

Manufacturer Part Number
PSMN2R0-30YL,115
Description
MOSFET N-CH 30V 100A LFPAK
Manufacturer
NXP Semiconductors
Series
TrenchMOS™r
Datasheet

Specifications of PSMN2R0-30YL,115

Package / Case
LFPak-4
Fet Type
MOSFET N-Channel, Metal Oxide
Fet Feature
Logic Level Gate
Rds On (max) @ Id, Vgs
2 mOhm @ 15A, 10V
Drain To Source Voltage (vdss)
30V
Current - Continuous Drain (id) @ 25° C
100A
Vgs(th) (max) @ Id
2.15V @ 1mA
Gate Charge (qg) @ Vgs
64nC @ 10V
Input Capacitance (ciss) @ Vds
3980pF @ 12V
Power - Max
97W
Mounting Type
Surface Mount
Minimum Operating Temperature
- 55 C
Configuration
Single
Transistor Polarity
N-Channel
Resistance Drain-source Rds (on)
2 mOhms
Drain-source Breakdown Voltage
30 V
Gate-source Breakdown Voltage
20 V
Continuous Drain Current
100 A
Power Dissipation
97 W
Maximum Operating Temperature
+ 175 C
Mounting Style
SMD/SMT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
568-4679-2
934063069115
PSMN2R0-30YL T/R
NXP Semiconductors
PSMN2R0-30YL
Product data sheet
Fig 13. Normalized drain-source on-state resistance
Fig 15. Gate-source voltage as a function of gate
a
V
1.5
0.5
(V)
10
GS
2
1
0
8
6
4
2
0
−60
factor as a function of junction temperature
charge; typical values
0
V
DS
20
0
= 12 (V)
60
40
V
DS
120
60
= 19 (V)
All information provided in this document is subject to legal disclaimers.
Q
003aac473
T
G
j
(nC)
( ° C)
03aa27
180
80
Rev. 4 — 10 March 2011
N-channel 30 V 2 mΩ logic level MOSFET in LFPAK
Fig 14. Gate charge waveform definitions
Fig 16. Input, output and reverse transfer capacitances
(pF)
5000
4000
3000
2000
1000
C
0
10
as a function of drain-source voltage; typical
values
V
-1
V
V
V
GS(pl)
DS
GS(th)
GS
C
C
C
Q
iss
oss
rss
GS1
I
1
Q
D
PSMN2R0-30YL
GS
Q
GS2
Q
G(tot)
Q
GD
10
© NXP B.V. 2011. All rights reserved.
V
DS
003aaa508
003aac478
(V)
10
2
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