BCM5208KPF Broadcom, BCM5208KPF Datasheet - Page 14

• Manufacturer Part Number: BCM5208KPF
• Manufacturer: Broadcom

Specifications of BCM5208KPF

• Number Of Receivers: 4
• Data Rate: 10/100Mbps
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (min): 3.14V
• Mounting: Surface Mount
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Lead Free Status / RoHS Status: Not Compliant

n BCM5208
SERIAL LED MODES
The BCM5208 supports several modes for providing LED and interrupt information as a serial bit stream. The LED data is
presented on a single pin with a second pin providing a shift clock and a third providing framing. When the Serial LED mode
is enabled, pin 182 becomes the bit clock output, pin 183 becomes the data output and pin 184 provides the framing pulse.
After the Serial LED mode is enabled, several options for bit format become available. If no action is taken, bits will be
shifted out as shown in the top line of the table below. If the INTR bit (bit 14 of MII Register 1Ah) is set, data will be shifted
out as shown in the Interrupt row of the table. If the FDXLED bit (bit 15 of MII Register 1Ah) is set, data will be shifted out
as shown in the Full-Duplex row of the table.
In each mode, 24 bits comprise a frame. Bits are shifted in the order shown in the table below, with those bits in the column
marked BIT 0 leaving the chip first and those in the column marked BIT 5 leaving the chip later in time. The sequence will
repeat 4 times between frame pulses to provide data for each PHY in the quad device. Bits are numbered from 0 to 5;
frames are numbered from 1 to 4. Therefore, bit 0 of PHY 1 is the first bit out of the frame, and bit 5 of PHY 4 is the 24th.
bit out of the frame.
Data is shifted out on the falling edge of the shift clock which is approximately 1 MHz. Data will be valid on the rising edge
of the shift clock. The framing pulse is high during the bit 0 time of frame1. For timing information, see Table 37 and Figure
11.
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A Global Interrupt indicates an interrupt from any of the 4 slices ORed together; a Slice Interrupt is from one of the 4 PHYs.
OPTION
Normal
Interrupt
Full-Duplex
MII REG 1AH
Bit 14 =0
Bit 15 =0
Bit 14 =1
Bit 15 =0
Bit 14 =0
Bit 15 =1
BIT 5
FDX
FDX
FDX
Table 3: Serial LED Mode Bit Framing
B r o a d c o m C o r p o r a t i o n
BIT 4
1
Global Interrupt
1
BIT 3
Speed
Speed
Speed
BIT 2
Link
Link
Link
BIT 1
Transmit
Slice Interrupt
FDX
Document 5208-DS03-R¥¥¥¥¥
November 3, 1999
BIT 0
Receive
Activity
Activity