BCM5208KPF Broadcom, BCM5208KPF Datasheet - Page 27

• Manufacturer Part Number: BCM5208KPF
• Manufacturer: Broadcom

Specifications of BCM5208KPF

• Number Of Receivers: 4
• Data Rate: 10/100Mbps
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (min): 3.14V
• Mounting: Surface Mount
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Lead Free Status / RoHS Status: Not Compliant

November 3, 1999
ISOLATE. Each individual PHY may be isolated from its Media Independent Interface by writing a “1” to bit 10 of the Control
Register. All MII outputs will be tri-stated and all MII inputs will be ignored. Since the MII management interface is still active,
the isolate mode may be cleared by writing a “0” to bit 10 of the control register, or by resetting the chip. When this bit is
read, it will return a “1” when the chip is in isolate mode, otherwise it will return a “0”.
RESTART AUTO-NEGOTIATION. Bit 9 of the Control Register is a self-clearing bit that allows the Auto-Negotiation
process to be restarted, regardless of the current status of the Auto-Negotiation state machine. In order for this bit to have
an effect, Auto-Negotiation must be enabled. Writing a “1” to this bit restarts the Auto-Negotiation, while writing a “0” to this
bit has no effect. Since the bit is self-clearing after only a few cycles, it always returns a “0” when read. The operation of
this bit is identical to bit 9 of the Auxiliary Multiple PHY Register.
DUPLEX MODE. By default, the BCM5208 powers up in half-duplex mode. The chip can be forced into full-duplex mode
by writing a “1” to bit 8 of the Control Register while Auto-Negotiation is disabled. Half-duplex mode can be resumed by
writing a “0” to bit 8 of the control register, or by resetting the chip.
COLLISION TEST. The COL pin may be tested during loopback by activating the Collision Test mode. While in this mode,
asserting TXEN will cause the COL output to go high within 512 bit times. Deasserting TXEN will cause the COL output to
go low within 4 bit times. Writing a “1” to bit 7 of the Control Register enables the Collision Test mode. Writing a “0” to this
bit or resetting the chip disables the Collision Test mode. When this bit is read, it will return a “1” when the Collision Test
mode has been enabled, otherwise it will return a “0”. This bit should only be set while in loopback test mode.
RESERVED BITS. All reserved MII register bits must be written as “0” at all times. Ignore the BCM5208 output when these
bits are read.
MII STATUS REGISTER
The MII status register bit descriptions are shown in Table 8.
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BIT
15
14
13
12
11
10:7
6
5
4
3
2
1
0
Note: R/W = Read/Write, RO = Read only, SC = Self Clear, LL = Latched Low, LH = Latched High, (LL and LH clear after
read operation )
NAME
100BASE-T4 Capability
100BASE-TX FDX Capability
100BASE-TX Capability
10BASE-T FDX Capability
10BASE-T Capability
Reserved
MF Preamble Suppression
Auto-Negotiation Complete
Remote Fault
Auto-Negotiation Capability
Link Status
Jabber Detect
Extended Capability
Table 8: MII Status Register (Address 01d, 01h)
R/W
RO
RO
RO
RO
RO
RO
R/W
RO
RO
LH
RO
RO
LL
RO
LH
RO
B r o a d c o m C o r p o r a t i o n
DESCRIPTION
0 = Not 100BASE-T4 capable
1 = 100BASE-TX full-duplex capable
1 = 100BASE-TX half-duplex capable
1 = 10BASE-T full-duplex capable
1 = 10BASE-T half-duplex capable
Ignore when Read
1 = Preamble may be suppressed
0 = Preamble always required
1 = Auto-Negotiation process completed
0 = Auto-Negotiation process not completed
1 = Far-end fault condition detected
0 = No far-end fault condition detected
1 = Auto-Negotiation capable
0 = Not Auto-Negotiation capable
1 = Link is up (Link Pass state)
0 = Link is down (Link Fail state)
1 = Jabber condition detected
0 = No jabber condition detected
1 = Extended register capable
n BCM5208
DEFAULT
0
1
1
1
1
0
0
0
0
1
0
0
1
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