BCM5208KPF Broadcom, BCM5208KPF Datasheet - Page 23

• Manufacturer Part Number: BCM5208KPF
• Manufacturer: Broadcom

Specifications of BCM5208KPF

• Number Of Receivers: 4
• Data Rate: 10/100Mbps
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (min): 3.14V
• Mounting: Surface Mount
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Lead Free Status / RoHS Status: Not Compliant

November 3, 1999
MEDIA INDEPENDENT INTERFACE (MII) MANAGEMENT INTERFACE: REGISTER PROGRAMMING
The BCM5208 fully complies with the IEEE 802.3u Media Independent Interface (MII) specification. The MII management
interface registers of each port are serially written-to and read-from using a common set of MDIO and MDC pins. A single
clock waveform must be provided to the BCM5208 at a rate of 0-12.5 MHz through the MDC pin. The serial data is
communicated on the MDIO pin. Every MDIO bit must have the same period as the MDC clock. The MDIO bits are latched
on the rising edge of the MDC clock.
See Table 5 for the fields in every MII read or write instruction frame.
Preamble (PRE). Thirty two consecutive “1” bits must be sent through the MDIO pin to the BCM5208 to signal the
beginning of an MII instruction. Fewer than 32 “1” bits will cause the remainder of the instruction to be ignored.
Start of Frame (ST). A “01” pattern indicates that the start of the instruction follows.
Operation Code (OP). A READ instruction is indicated by “10”, while a WRITE instruction is indicated by “01”.
PHY Address (PHYAD). A 5-bit PHY address follows next, with the MSB transmitted first. The PHY address allows a single
MDIO bus to access multiple PHY chips. The BCM5208 supports the full 32-PHY address space with PHYAD[4:2] input-
pin controlled and PHYAD[1:0] internally decoded to select one of the four transceivers.
Register Address (REGAD). A 5-bit Register Address follows, with the MSB transmitted first. The register map of the
BCM5208, containing register addresses and bit definitions, are provided on the following pages.
Turnaround (TA). The next two bit times are used to avoid contention on the MDIO pin when a Read operation is
performed. For a Write operation, “10” must be sent to the BCM5208 chip during these two bit times. For a Read operation,
the MDIO pin must be placed into High-Impedance during these two bit times. The chip will drive the MDIO pin to “0” during
the second bit time.
Data. The last 16 bits of the frame are the actual data bits. For a Write operation, these bits are sent to the BCM5208,
whereas, for a Read operation, these bits are driven by the BCM5208. In either case, the MSB is transmitted first.
When writing to the BCM5208, the data field bits must be stable 10 ns before the rising-edge of MDC, and must be held
valid for 10 ns after the rising edge of MDC. When reading from the BCM5208, the data field bits are valid after the rising-
edge of MDC until the next rising-edge of MDC.
Idle. A high impedance state of the MDIO line. All tri-state drivers are disabled and the PHY’s pull-up resistor pulls the MDIO
line to logic “1”. Note that at least one or more clocked idle states are required between frames.Following are two examples
of MII write and read instructions:
•
•
For the MII read operation, the BCM5208 will drive the MDIO line during the TA and Data fields (the last 17 bit times). A
final 65th clock pulse must be sent to close the transaction, and cause a write operation to take place.
MII REGISTER MAP SUMMARY
Table 6 contains the MII register summary for each port of the BCM5208. The register addresses are specified in hex form,
and the name of register bits have been abbreviated. When writing to the reserved bits, always write a “0” value, and when
reading from these bits, ignore the output value. Never write any value to an undefined register address. The reset value
of the registers are shown in the INIT column.
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OPERATION
READ
WRITE
To put a transceiver with PHY address 00001 into Loopback mode, the following MII write instruction must be issued:
1111 1111 1111 1111 1111 1111 1111 1111
To determine if a PHY is in the link pass state, the following MII read instruction must be issued:
1111 1111 1111 1111 1111 1111 1111 1111
1 ... 1
1 ... 1
PRE
ST
01
01
SECTION 5: REGISTER SUMMARY
Table 5: MII Management Frame Format
OP
01
10
0101 00001 00000 10 0100 0000 0000 0000 1...
0110 00001 00001 ZZ ZZZZ ZZZZ ZZZZ ZZZZ 1...
PHYAD
AAAAA
AAAAA
B r o a d c o m C o r p o r a t i o n
REGAD
RRRRR
RRRRR
TA
ZZ
Z0
10
D ... D
D ... D
DATA
Z ... Z
IDLE
Z
Z
Z
DIRECTION
Driven to BCM5208
Driven by BCM5208
Driven to BCM5208
n BCM5208
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