BCM5208KPF Broadcom, BCM5208KPF Datasheet - Page 38

• Manufacturer Part Number: BCM5208KPF
• Manufacturer: Broadcom

Specifications of BCM5208KPF

• Number Of Receivers: 4
• Data Rate: 10/100Mbps
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (min): 3.14V
• Mounting: Surface Mount
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Lead Free Status / RoHS Status: Not Compliant

n BCM5208
INTERRUPT REGISTER
Table 21 shows the bit descriptions for the interrupt register.
FDX LED ENABLE. Setting this bit enables the FDX LED mode. Bits 14 and 15 of this register are mutually exclusive. Only
one may be set at a time. When FDXLED mode is enabled, XMTLED# becomes FDXLED# and RCVLED# becomes
ACTLED#.
INTERRUPT ENABLE. Setting this bit enables Interrupt Mode. Bits 14 and 15 of this register are mutually exclusive. Only
one may be set at a time. When Interrupt Mode is enabled, XMTLED# becomes INTR# and RCVLED# becomes ACTLED#.
Side Note: if both bits 14 and 15 are set at the same time, the FDXLED# will override the INTR# output, even though the
interrupt’s FDX, SPD, and LINK change status bits will behave as in normal interrupt operation.
FDX MASK. When this bit is set, changes in Duplex mode will not generate an interrupt.
SPD MASK. When this bit is set, changes in operating speed will not generate an interrupt.
LINK MASK. When this bit is set, changes in Link status will not generate an interrupt.
INTERRUPT MASK. Master Interrupt Mask. When this bit is set, no interrupts will be generated, regardless of the state of
the other MASK bits.
FDX CHANGE. A “1” indicates a change of Duplex status since last register read. Register read clears the bit.
SPD CHANGE. A “1” indicates a change of Speed status since last register read. Register read clears the bit.
LINK CHANGE. A “1” indicates a change of Link status since last register read. Register read clears the bit.
INTERRUPT STATUS. Represents status of the INTR# pin. A “1” indicates that the interrupt mask is off and that one or
more of the change bits are set. Register read clears the bit.
Page 30
Note: R/W = Read/Write, RO = Read only, SC = Self Clear, LL = Latched Low, LH = Latched High (LL and LH clear after
BIT
15
14
13:12
11
10
9
8
7:4
3
2
1
0
read operation)
FDX LED Enable
INTR Enable
Reserved
FDX Mask
SPD Mask
LINK Mask
INTR Mask
Reserved
FDX Change
SPD Change
LINK Change
INTR Status
NAME
Table 21: Interrupt Register (Address 26d, 1Ah)
R/W
R/W
R/W
RO
R/W
R/W
R/W
R/W
RO
RO
LH
RO
LH
RO
LH
RO
LH
B r o a d c o m C o r p o r a t i o n
DESCRIPTION
Full-Duplex LED Enable
Interrupt Enable
Full-Duplex Interrupt Mask
SPEED Interrupt Mask
LINK Interrupt Mask
Master Interrupt Mask
Duplex Change Interrupt
Speed Change Interrupt
Link Change Interrupt
Interrupt Status
Document 5208-DS03-R¥¥¥¥¥
November 3, 1999
DEFAULT
0
0
0
1
1
1
1
0
0
0
0
0