BCM5208KPF Broadcom, BCM5208KPF Datasheet - Page 35

• Manufacturer Part Number: BCM5208KPF
• Manufacturer: Broadcom

Specifications of BCM5208KPF

• Number Of Receivers: 4
• Data Rate: 10/100Mbps
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (min): 3.14V
• Mounting: Surface Mount
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Lead Free Status / RoHS Status: Not Compliant

November 3, 1999
AUXILIARY CONTROL/STATUS REGISTER
Table 19 shows the auxiliary control/status register bit descriptions.
JABBER DISABLE. 10BASE-T operation only. Bit 15 of the Auxiliary Control Register allows the user to disable the Jabber
Detect function, defined in the IEEE standard. This function shuts off the transmitter when a transmission request has
exceeded a maximum time limit. By writing a “1” to bit 15 of the Auxiliary Control Register, the Jabber Detect function is
disabled. Writing a “0” to this bit or resetting the chip restores normal operation. Reading this bit returns the value of Jabber
Detect Disable.
LINK DISABLE. Writing a “1” to bit 14 of the Auxiliary Control Register allows the user to disable the Link Integrity state
machines, and place the BCM5208 into forced Link Pass status. Writing a “0” to this bit or resetting the chip restores the
Link Integrity functions. Reading this bit returns the value of Link Integrity Disable.
TEST MODE. Active-high test mode control bit. Must be written with “0” for normal operation.
HSQ AND LSQ. Extend or decrease the squelch levels for detection of incoming 10BASE-T data packets. The default
squelch levels implemented are those defined in the IEEE standard. The high- and low-squelch levels are useful for
situations where the IEEE-prescribed levels are inadequate. The squelch levels are used by the CRS/LINK block to filter
out noise and recognize only valid packet preambles and link integrity pulses. Extending the squelch levels allows the
BCM5208 to operate properly over longer cable lengths. Decreasing the squelch levels may be useful in situations where
there is a high level of noise present on the cables. Reading these two bits returns the value of the squelch levels.
EDGE RATE. Control bits used to program the transmit DAC output edge rate in 100BASE-TX mode. These bits are
logically AND’ed with the ER[1:0] input pins to produce the internal edge-rate controls (Edge_Rate[1] AND ER[1],
Edge_Rate[0] AND ER[0]).
Document 5208-DS03-R¥¥¥¥¥
BIT
15
14
13:8
7:6
5:4
3
2
1
0
NAME
Jabber Disable
Link Disable
Reserved
HSQ : LSQ
Edge Rate [1:0]
Auto-Negotiation Indicator
Force 100/10 Indication
Speed Indication
Full-Duplex Indication
Table 19: Auxiliary Control/Status Register (Address 24d, 18h)
R/W
R/W
R/W
RO
R/W
R/W
RO
RO
RO
RO
B r o a d c o m C o r p o r a t i o n
DESCRIPTION
1= Jabber function disabled in PHY
0 = Jabber function enabled in PHY
1= Link Integrity test disabled in PHY
0 = Link Integrity test is enabled in PHY
Ignore when Read
These two bits define the Squelch Mode of the
10BASE-T Carrier Sense mechanism:
00 = normal squelch
01 = low squelch
10 = high squelch
11 = not allowed
00 = 1 ns
01 = 2 ns
10 = 3 ns
11 = 4 ns
1 = Auto-Negotiation activated
0 = Speed forced manually
1 = Speed forced to 100BASE-X
0 = Speed forced to 10BASE-T
1 = 100BASE-X
0 = 10BASE-T
1 = Full-duplex active
0 = Full-duplex not active
n BCM5208
DEFAULT
0
0
000000
00
11
1
1
0
0
Page 27