AM79C874VC AMD (ADVANCED MICRO DEVICES), AM79C874VC Datasheet - Page 14

• Manufacturer Part Number: AM79C874VC
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM79C874VC

• Lead Free Status / RoHS Status: Not Compliant

MDC
Management Data Clock
This clock is sourced by the MAC and is used to
synchronize MDIO data. When management is not
used, this pin should be tied to ground.
INTR
Interrupt
This pin is used to signal an interrupt to the MAC. The
pin will be forced high or low (normally high imped-
ance) to signal an interrupt depending upon the value
of the INTR_LEVL bit, MII Register 16, bit 14. The
events which trigger an interrupt can be programmed
via the Interrupt Control Register (Register 17).
TECH_SEL[2:0]
Technology Select
The Technology Select pins, in conjunction with the
ANEGA pin, set the speed and duplex configurations
for the device on the rising edge of reset. These capa-
bilities are reflected in MII Register 1 and MII Register
4. Table 6 lists the possible configurations for the de-
vice. If the input is listed as LOW, the pin should be
pulled to ground via a 1-4.7 kΩ resistor on the rising
edge of reset. If the input is listed as HIGH, the pin can
be left unconnected.
Note: By
TECH_SEL[2:0] pins and the ANEGA pin, using the
MDC/MDIO management interface pins becomes op-
tional. The device’s speed, duplex, and auto-negotia-
t i o n c a pa b il i t i e s a r e s e t v i a h a r d w a r e . I f t h e
management interface is used, the registers cannot be
set to a higher capability than the hard-wired setting.
The highest capabilities are Full Duplex, 100 Mbps,
and Auto-Negotiation enabled.
ANEGA
Auto-Negotiation Ability
When this pin is pulled to ground via a 1-4.7 kΩ resis-
tor, on the rising edge of reset, Auto-Negotiation is dis-
abled. When this pin is left unconnected, on the rising
edge of reset, Auto-Negotiation is enabled. Note that
this pin acts in conjunction with Tech_Sel[2:0] on the
rising edge of reset. Refer to Table 3 to determine the
desired configuration for the device.
In 100BASE-FX mode, ANEGA should be pulled to
ground.
Note: By
TECH_SEL[2:0] pins and the ANEGA pin, using the
MDC/MDIO management interface pins becomes op-
tional. The device’s speed, duplex, and auto-negotia-
t i o n c a pa b il i t i e s a r e s e t v i a h a r d w a r e . I f t h e
management interface is used, the registers cannot be
set to a higher capability than the hard-wired setting.
The highest capabilities are Full Duplex, 100 Mbps,
and Auto-Negotiation enabled.
14
using
using
resistors
resistors
Output, High Impedance
to
to
hard
hard
Input, Pull-Up
Input, Pull-Up
wire
wire
Input
D A T A
Am79C874
the
the
RPTR
Repeater Mode
This pin should be tied to ground via a 1-4.7 kΩ resistor
if repeater mode is to be disabled. When this pin is
pulled high via a 1-4.7 kΩ resistor, repeater mode will
be enabled. Repeater mode can also enabled via MII
Register 16, bit 15. In this mode, the port is set to Half
Duplex and SQE is not performed.
LED Port Pins
LEDRX/LED_SEL
Receive LED/LED Configuration Select
When this pin is pulled low via a 1 kΩ resistor, on the
rising edge of reset, the advanced LED configuration is
enabled. If there is no pull-down resistor present, on
the rising edge of reset, the standard LED configuration
is enabled.
After the rising edge of reset this pin controls the Re-
ceive LED. This pin toggles between high and low
when data is received. When the device is operating in
the standard LED mode, refer to Figure 5 in the LED
Port Configuration section. When the device is operat-
ing in the advanced LED mode, refer to Table 9 and
Figure 6 in the LED Port Configuration section.
LEDCOL/SCRAM_EN
Collision LED/Scrambler Enable
When this pin is pulled low via a 1-kΩ resistor, on the
rising edge of reset, the scrambler/descrambler is dis-
abled. If no pull-down resistor is present, on the rising
edge of reset, the scrambler/descrambler is enabled.
After the rising edge of reset this pin controls the Colli-
sion LED. This pin toggles between high and low when
there is a collision in half-duplex operation. In full-
duplex operation this pin is inactive. When the device
is operating in the standard LED mode, refer to Figure
5 in the LED Port Configuration section. When the de-
vice is operating in the advanced LED mode, see Fig-
ure 6.
LEDLNK/LED_10LNK/LED_PCSBP_SD
Link LED/7-Wire Link LED/PCSBP Signal Detect
W h e n a li n k i s e s ta b l i s h e d i n 1 0 0 B A S E - X o r
10BASE-T mode, this pin will assume a logic low level.
When a link is established in 7-Wire mode, this pin will
assume a logic high level.
When in PCS Bypass mode, this pin assumes a logic
high level indicating Signal Detect.
Refer to Figure 4 in the LED Port Configuration section
if the device is operating in the standard LED mode.
See Figure 5 if the device is operating in the advanced
LED mode.
S H E E T
Input/Output, Pull-Up
Input/Output, Pull-Up
22235K
Output
Input