AM79C874VC AMD (ADVANCED MICRO DEVICES), AM79C874VC Datasheet - Page 17

• Manufacturer Part Number: AM79C874VC
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM79C874VC

• Lead Free Status / RoHS Status: Not Compliant

■ RXD (receive data) is a nibble (4 bits) of data that is
■ RX_CLK (receive clock) output to the MAC reconcil-
■ RX_DV (receive data valid) input from the PHY to
■ RX_ER (receive error) transitions synchronously
■ CRS (carrier sense) is asserted by the PHY when
7-Wire (GPSI) Mode
7-Wire (GPSI) mode uses the existing MII pins, but
data is transferred only on TXD[0] and RXD[0]. This
mode is used in a General Purpose Serial Interface
(GPSI) configuration for 10BASE-T. If the GPIO[0] pin
is LOW at the rising edge of reset, then GPSI mode is
selected. For this configuration, TX_CLK runs at 10
MHz. When the cable is unplugged, 10TXCLK ceases
operation. Note that 7-wire mode does not define the
use of Auto-Negotiation or MDC/MDIO.
The MII pins that relate to 7-wire (GPSI) mode are
shown in the following table. The unused input pins in
this mode should be tied to ground through a 1 kΩ re-
sistor. The RPTR pin must be connected to GND.
22235K
Table 4. MII Pins that Relate to 10 Mbps 7-Wire
RX_CLK/10RXCLK
TX_CLK/10TXCLK
sampled by the reconciliation sublayer synchro-
nously with respect to RX_CLK. For each RX_CLK
period which RX_DV is asserted, RXD[3:0] are
transferred from the PHY to the MAC reconciliation
sublayer.
iation sublayer is a continuous clock (during LINK
only) that provides the timing reference for the
transfer of the RX_DV, RXD, and RX_ER signals.
indicate the PHY is presenting recovered and de-
coded nibbles to the MAC reconciliation sublayer.
To interpret a receive frame correctly by the recon-
ciliation sublayer, RX_DV must encompass the
frame starting no later than the Start-of-Frame de-
limiter and excluding any End-Stream delimiter.
with respect to RX_CLK. RX_ER will be asserted
for 1 or more clock periods to indicate to the recon-
ciliation sublayer that an error was detected some-
where in the frame being received by the PHY.
either the transmit or receive medium is non-idle
and deasserted by the PHY when the transmit and
receive medium are idle.
TX_EN/10TXEN
RXD[0] /10RXD
TXD[0]/10TXD
MII Pin Name
COL/10COL
RXD[3:1]
TXD[3:1]
TX_ER
(GPSI) mode
Transmit Serial Data Stream
Receive Serial Data Stream
Transmit Enable
Collision Detect
Transmit Clock
7-Wire (GPSI)
Receive Clock
Not used
Not used
Not used
D A T A
S H E E T
Am79C874
Note: CRS ends one and one-half bit times after the
last data bit. The effect is one or two dribbling bits on
every packet. All MACs truncate packets to eliminate
the dribbling bits. The only noticeable effect is that all
CRC errors are recorded as framing errors.
Use the TECH_SEL[2:0] to select the desired 10BASE-
T operation.
5B Symbol Mode
The purpose of the 5B Symbol mode is to provide a
way for the MAC to do the 4B/5B encoding/decoding
and scrambling/descrambling in 100 Mbps operation.
In 10 Mbps operation, the MII signals are not used. In-
stead, the NetPHY-1LP device operates as a
10BASE-T transceiver, providing received data to the
MAC over a serial differential pair (see PCSBP pin).
The MAC uses two serial differential pairs to provide
transmit data to the NetPHY-1LP device, where the two
differential pairs are combined in the NetPHY-1LP de-
vice to compensate for inter-symbol interference on the
twisted pair medium.
100BASE-X Block
The functions performed by the device include encod-
ing of MII 4-bit data (4B/5B), decoding of received code
groups (5B/4B), generating carrier sense and collision
detect indications, serialization of code groups for
transmission, de-serialization of serial data upon re-
ception, mapping of transmit, receive, carrier sense,
and collision at the MII interface, and recovery of clock
from the incoming data stream. It offers stream cipher
scrambling and descrambling capability for 100BASE-
TX applications.
I n t h e t r a n s m i t d a t a p a t h f o r 1 0 0 M b ps , t h e
NetPHY-1LP transceiver receives 4-bit (nibble) wide
data across the MII at 25 million nibbles per second.
For 100BASE-TX applications, it encodes and scram-
bles the data, serializes it, and transmits an MLT-3 data
stream to the media via an isolation transformer. For
100BASE-FX applications, it encodes and serializes
the data and transmits a Pseudo-ECL (PECL) data
stream to the fiber optic transmitter. See Figure 1.
In the receive data path for 100 Mbps, the NetPHY-1LP
transceiver receives an MLT-3 data stream from the
network. For 100BASE-TX, it then recovers the clock
from the data stream, de-serializes the data stream,
and descrambles/decodes the data stream (5B/4B) be-
fore presenting it at the MII interface.
Table 4. MII Pins that Relate to 10 Mbps 7-Wire
MII Pin Name
CRS/10CRS
RX_ER
(GPSI) mode (continued)
Carrier Sense Detect
7-Wire (GPSI)
Not used
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