AM79C874VC AMD (ADVANCED MICRO DEVICES), AM79C874VC Datasheet - Page 25

• Manufacturer Part Number: AM79C874VC
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM79C874VC

• Lead Free Status / RoHS Status: Not Compliant

1. MII Register 0 (speed and duplex bits) must be set by the MAC to achieve a link.
2. When Auto-Negotiation is enabled, these bits can be written but will be ignored by the PHY.
3. The advertised abilities in MII Register 4 cannot exceed the abilities of MII Register 1. Auto-Negotiation should always
Far-End Fault
Auto-Negotiation provides a remote fault capability for
detecting asymmetric link failure. Since 100Base-FX
systems do not use Auto-Negotiation, an alternative,
in-band signaling scheme, Far-End Fault is used to sig-
nal remote fault conditions. Far-End Fault is a stream
of 63 consecutive 1s followed by one logic 0. This pat-
tern is repeated three times. A Far-End Fault will be
signaled under three conditions: (1) when no activity is
received from the link partner, (2) when the clock recov-
ery circuit detects signal error or PLL lock error, and (3)
when the management entity sets the transmit FEF bit
(MII Register 21, bit 7).
The Far-End Fault mechanism defaults to enable
100BASE-FX mode and disable 100BASE-TX and
10BASE-T modes, and may be controlled by software
after reset.
SQE (Heartbeat)
When the SQE test is enabled, a COL signal with a 5-
15 bit time pulse will be issued after each transmitting
packet. SQE is enabled and disabled via MII Register
16, bit 11.
Loopback Operation
A local loopback and remote loopback are provided for
testing. They can be enabled by writing to either MII
22235K
ANEGA
remain enabled. Hardware settings override software settings in registers.
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
(Hardwired on Board)
Tech[2]
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
Tech[1]
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
Tech[0]
Table 6. Speed and Duplex Capabilities
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
D A T A
Speed
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
No
No
No
No
No
S H E E T
Am79C874
1
1
2
2
2
2
2
2
2
3
(Changeable in MII Register 0)
Register 0, bit 14 (Loopback) or MII Register 21, bit 3
(EN_RPBK).
The local loopback routes transmitted data at the out-
put of NRZ-to-NRZI conversion module back to the
receiving path’s clock and data recovery module for
connection to PCS in 5 bits symbol format. This loop-
back is used to check all the connections at the 5-bit
symbol bus side and the operation of analog phase
locked loop. In local loopback, the SD output is forced
to logic one and TX± outputs are tristated.
During local loopback, a 10-Mbps link is sent to the link
partner. In either 100BASE-TX or 10BASE-T loopback
mode, the link for 10 Mbps is forced (Register 21, bit
14) and is seen externally. If packets are transmitted
from the Device Under Test (DUT), the link between the
DUT and link partner is lost. Ceasing transmission
causes the link to go back up.
In order to perform a local loopback, one of the folllow-
ing procedures must be performed:
1. If ANEGA is already on, establish a link with a part-
2. If ANEGA is low/off, enable loopback bit 14.
In remote loopback, incoming data passes through the
equalizer and clock recovery, then loop back to NRZI/
MLT3 conversion module and out to the driver. This
Duplex
ner, and then enable bit 14 looback, or
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
No
No
No
No
No
1
1
2
2
2
2
2
2
2
2
ANEG-EN
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
No
No
No
No
No
No
No
3
3
3
3
3
3
3
3
No Capabilities, ANEG
No Capabilities, ANEG
All Capabilities, ANEG
100HD, 10HD, ANEG
Capabilities/ANEG
100FD/HD, ANEG
10FD/HD, ANEG
All Capabilities
All Capabilities
100HD, ANEG
10HD, ANEG
100HD
100HD
100FD
100FD
10HD
10FD
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