AM79C874VC AMD (ADVANCED MICRO DEVICES), AM79C874VC Datasheet - Page 23

• Manufacturer Part Number: AM79C874VC
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM79C874VC

• Lead Free Status / RoHS Status: Not Compliant

Ecliptek (EC-AT-25.000M, ECSM-AT-25.000M) and
Epson (MA-505-25.000M).
Alternatively, a crystal oscillator can be used to source
a clock on the REFCLK input. The oscillator must be 25
MHz ±50 ppm with a 40% to 60% duty cycle. Recom-
mended parts are Ecliptek (EC1300 HSTS-25.000M)
and Epson (MA506-25.000 MHz).
Note that PLL oscillators cannot be used for XTL± or
REFCLK.
Using crystals or oscillators beyond these specifica-
tions will not guarantee successful operation of the
NetPHY-1LP.
10BASE-T Block
The NetPHY-1LP transceiver incorporates the
10BASE-T physical layer functions, including clock re-
covery (ENDEC), MAUs, and transceiver functions.
The NetPHY-1LP transceiver receives 10-Mbps data
from the MAC, switch, or repeater across the MII at 2.5
million nibbles per second (parallel), or 10 million bits
per second (serial). It then Manchester encodes the
data before transmission to the network.
Refer to Figure 4 for the 10BASE-T transmit and re-
ceive data paths.
Figure 4. 10BASE-T Transmit /Receive Data Paths
Twisted Pair Transmit Process
In 10BASE-T mode, Manchester code will be gener-
ated by the 10BASE-T core logic, which will then be
synthesized through the output waveshaping driver.
This will help reduce any EMI emission, eliminating the
need for an external filter. Data transmission over the
22235K
Clock
Manchester
Encoder
TX Driver
TX±
Data
(Register 0)
Loopback
Clock
Manchester
RX Driver
Decoder
Squelch
Circuit
RX±
Data
D A T A
22236G-6
S H E E T
Am79C874
10BASE-T medium requires use of the integrated
10BASE-T MAU and uses the differential driver cir-
cuitry on the TX± pins.
TX± is a differential twisted-pair driver. When properly
terminated, TX± meets the transmitter electrical re-
quirements for 10BASE-T transmitters as specified in
IEEE 802.3, Section 14.3.1.2. The load is a twisted pair
cable that meets IEEE 802.3, Section 14.4.
The TX± signal is filtered on the chip to reduce har-
monic content per Section 14.3.2.1 (10BASE-T). Since
filtering is performed in silicon, TX± can be connected
directly to a standard transformer. External filtering
modules are not needed
Twisted Pair Receive Process
In 10BASE-T mode, the signal first passes through a
third order Elliptical filter, which filters all the noise from
the cable, board, and transformer. This eliminates the
need for a 10BASE-T external filter. A Manchester de-
coder and a Serial-to-Parallel converter then follow to
generate the 4-bit nibble in MII mode.
RX+ ports are differential twisted-pair receivers. When
properly terminated, each RX+ port meets the electrical
requirements for 10BASE-T receivers as specified in
IEEE 802.3, Section 14.3.1.3. Each receiver has inter-
nal filtering and does not require external filter modules
or common mode chokes.
Signals appearing at the RX± differential input pair are
routed to the internal decoder. The receiver function
meets the propagation delays and jitter requirements
specified by the 10BASE-T standard. The receiver
squelch level drops to half its threshold value after un-
squelch to allow reception of minimum amplitude sig-
nals and to mitigate carrier fade in the event of worst
case signal attenuation and crosstalk noise conditions.
Twisted Pair Interface Status
The NetPHY-1LP transceiver will power up in the Link
Fail state. The Auto-Negotiation algorithm will apply to
allow it to enter the Link Pass state. A link-pulse detec-
tion circuit constantly monitors the RX± pins for the
presence of valid link pulses. In the Link Pass state, re-
ceive activity which passes the pulse width/amplitude
requirements of the RX± inputs cause the PCS Control
block to assert Carrier Sense (CRS) signal at the MII in-
terface.
Collision Detect Function
Simultaneous activity (presence of valid data signals)
from both the internal encoder transmit function and
the twisted pair RX± pins constitutes a collision,
thereby causing the PCS Control block to assert the
COL pin at the MII.
Collisions cause the PCS Control block to assert the
Carrier Sense (CRS) and Collision (COL) signals at the
MII. In the Link Fail state, this block would cause the
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