AM79C874VC AMD (ADVANCED MICRO DEVICES), AM79C874VC Datasheet - Page 37

• Manufacturer Part Number: AM79C874VC
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM79C874VC

• Lead Free Status / RoHS Status: Not Compliant

22235K
Reg
16
16
16
16
16
16
16
16
16
16
16
16
16
13:12 Reserved
3:1
Bit
15
14
10
11
9
8
7
6
5
4
0
Name
Repeater
INTR_LEVL
SQE Test Inhibit
10BASE-T
Loopback
GPIO_1 Data
GPIO_1 DIR
GPIO_0 Data
GPIO_0 DIR
Auto polarity
Disable
Reverse Polarity
Reserved
Receive Clock
Control
Table 23. Miscellaneous Features Register (Register 16)
Description
1= Repeater mode, full-duplex is inactive, and CRS only
responds to receive activity. SQE test function is also disabled.
INTR will be active high if this register bit is set to 1. Pin requires
an external pull-down resistor.
INTR will be active low if this register bit is set to 0. Pin requires
an external pull-up resistor.
Write as 0, ignore when read.
1 = Disable 10BASE-T SQE testing.
0 = Enable 10BASE-T SQE testing. A COL pulse is generated
following the completion of a packet transmission.
1 = Enable normal loopback in 10BASE-T mode.
0 = Disable normal loopback in 10BASE-T mode.
When GPIO_1 DIR bit is set to 1, this bit reflects the value of the
GPIO[1] pin. When GPIO_1 DIR bit is set to 0, the value of this bit
will be presented on the GPIO[1] pin.
1 = GPIO[1] pin is an input.
0 = GPIO[1] pin is an output.
When GPIO_0 DIR bit is set to 1, this bit reflects the value of the
GPIO[0] pin. When GPIO[0] DIR bit is set to 0, the value of this bit
will be presented on the GPIO[0] pin.
1 = GPIO[0] pin is an input.
0 = GPIO[0] pin is an output.
1 = Disable auto polarity detection/correction.
0 = Enable auto polarity detection/correction.
When Register 16.5 is set to 0, this bit will be set to 1 if reverse
polarity is detected on the media. Otherwise, it will be 0.
When Register 16.5 is set to 1, writing a 1 to this bit will reverse
the polarity of the transmitter.
Note: Reverse polarity is detected either through eight inverted
NLPs or through a burst of an inverted FLP.
Write as 0, ignore when read.
Writing a 1 to this bit will shut off RX_CLK when incoming data is
not present and only if there is LINK present. RX_CLK will resume
activity one clock cycle prior to RX_DV going high, and shut off 64
clock cycles after RX_DV goes low.
A 0 indicates that RX_CLK runs continuously during LINK
whether data is received or not
In loopback and PCS bypass modes, writing to this bit does not
affect RX_CLK. Receive clock will be constantly active.
D A T A
S H E E T
Am79C874
Read/
Write
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RO
Default
Set by
RPTR
0
0
0
0
0
1
0
1
0
0
0
0
37